PR for llvm/llvm-project#55349 #194
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Map the IMPLEMENTOR ID 0xc0 (Ampere Computing) and CPU ID 0xac3 (Ampere1) to ampere1. Differential Revision: https://reviews.llvm.org/D117111 (cherry picked from commit 7e02bc5)
Add support for the Ampere Computing Ampere1 core. Ampere1 implements the AArch64 state and is compatible with ARMv8.6-A. Differential Revision: https://reviews.llvm.org/D117112 (cherry picked from commit 64816e6)
The initial support for the Ampere1 mistakenly signalled support for the MTE feature. However, the core does not include the optional MTE functionality. Update the target parser to not include MTE for Ampere1. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D125191 (cherry picked from commit 91b24b0)
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resolves llvm#55349