[RISCV] Allow libunwind to build for rv32e

[ArcaneNibble]

Don't try to save x16-x31 when using rv32e ISA

Note that I haven't actually tested yet whether or not unwinding actually works on rv32e, but the code as-is doesn't even build.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-libunwind

Author: R (ArcaneNibble)

Changes

Don't try to save x16-x31 when using rv32e ABI

Note that I haven't actually tested yet whether or not unwinding actually works on rv32e, but the code as-is doesn't even build.

---

Full diff: https://github.com/llvm/llvm-project/pull/98855.diff

2 Files Affected:

• (modified) libunwind/src/UnwindRegistersRestore.S (+4)
• (modified) libunwind/src/UnwindRegistersSave.S (+4)

diff --git a/libunwind/src/UnwindRegistersRestore.S b/libunwind/src/UnwindRegistersRestore.S
index 67d9e05711898..837cc8a8878d8 100644
--- a/libunwind/src/UnwindRegistersRestore.S
+++ b/libunwind/src/UnwindRegistersRestore.S
@@ -1169,7 +1169,11 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_riscv6jumptoEv)
     ILOAD x\i, (RISCV_ISIZE * \i)(a0)
   .endr
   // skip a0 for now
+#if defined(__riscv_abi_rve)
+  .irp i,11,12,13,14,15
+#else
   .irp i,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+#endif
     ILOAD x\i, (RISCV_ISIZE * \i)(a0)
   .endr
   ILOAD    x10, (RISCV_ISIZE * 10)(a0)   // restore a0
diff --git a/libunwind/src/UnwindRegistersSave.S b/libunwind/src/UnwindRegistersSave.S
index 5bf6055fe4147..30d94600bbb35 100644
--- a/libunwind/src/UnwindRegistersSave.S
+++ b/libunwind/src/UnwindRegistersSave.S
@@ -1108,7 +1108,11 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
 #
 DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
   ISTORE    x1, (RISCV_ISIZE * 0)(a0) // store ra as pc
+#if defined(__riscv_abi_rve)
+  .irp i,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+#else
   .irp i,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+#endif
     ISTORE x\i, (RISCV_ISIZE * \i)(a0)
   .endr
 

[ldionne]

This seems reasonable to me, but I have basically no knowledge of risvc or the rv32e ABI so I'll let someone else stamp this.

[ArcaneNibble]

ping? is there someone with the necessary knowledge to review this?

[ArcaneNibble]

ping?

[asb]

@lenary @kito-cheng is this something either of you might be able to help review?

[lenary]

I'm happy with this from a RISC-V arch/abi point of view.

[ArcaneNibble]

I don't have write access, someone else needs to decide to merge

[lenary]

@ArcaneNibble your contributions now definitely meet the threshold for commit access - please request it following the instructions in the Developer Policy: https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access (also take a read of the rest of the policy to understand how the processes are expected to work once you have it)