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[AMDGPU] Remove SIWholeQuadMode pass early exit #98450

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merged 3 commits into from
Jul 17, 2024
Merged

[AMDGPU] Remove SIWholeQuadMode pass early exit #98450

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a7356db
[AMDGPU] Remove SIWholeQuadMode pass early exit
perlfu Jul 11, 2024
627b345
Address comments:
perlfu Jul 14, 2024
f3317a0
Match previous conditions for variable live mask register introduction.
perlfu Jul 17, 2024
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50 changes: 27 additions & 23 deletions llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -219,11 +219,12 @@ class SIWholeQuadMode : public MachineFunctionPass {
void lowerBlock(MachineBasicBlock &MBB);
void processBlock(MachineBasicBlock &MBB, bool IsEntry);

void lowerLiveMaskQueries();
void lowerCopyInstrs();
void lowerKillInstrs(bool IsWQM);
bool lowerLiveMaskQueries();
bool lowerCopyInstrs();
bool lowerKillInstrs(bool IsWQM);
void lowerInitExec(MachineInstr &MI);
MachineBasicBlock::iterator lowerInitExecInstrs(MachineBasicBlock &Entry);
MachineBasicBlock::iterator lowerInitExecInstrs(MachineBasicBlock &Entry,
bool &Changed);

public:
static char ID;
Expand Down Expand Up @@ -1424,7 +1425,7 @@ void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, bool IsEntry) {
assert(!SavedNonStrictReg);
}

void SIWholeQuadMode::lowerLiveMaskQueries() {
bool SIWholeQuadMode::lowerLiveMaskQueries() {
for (MachineInstr *MI : LiveMaskQueries) {
const DebugLoc &DL = MI->getDebugLoc();
Register Dest = MI->getOperand(0).getReg();
Expand All @@ -1436,9 +1437,10 @@ void SIWholeQuadMode::lowerLiveMaskQueries() {
LIS->ReplaceMachineInstrInMaps(*MI, *Copy);
MI->eraseFromParent();
}
return !LiveMaskQueries.empty();
}

void SIWholeQuadMode::lowerCopyInstrs() {
bool SIWholeQuadMode::lowerCopyInstrs() {
for (MachineInstr *MI : LowerToMovInstrs) {
assert(MI->getNumExplicitOperands() == 2);

Expand Down Expand Up @@ -1493,9 +1495,10 @@ void SIWholeQuadMode::lowerCopyInstrs() {
*MRI, MI->getOperand(0)));
MI->setDesc(TII->get(CopyOp));
}
return !LowerToCopyInstrs.empty() || !LowerToMovInstrs.empty();
}

void SIWholeQuadMode::lowerKillInstrs(bool IsWQM) {
bool SIWholeQuadMode::lowerKillInstrs(bool IsWQM) {
for (MachineInstr *MI : KillInstrs) {
MachineBasicBlock *MBB = MI->getParent();
MachineInstr *SplitPoint = nullptr;
Expand All @@ -1511,6 +1514,7 @@ void SIWholeQuadMode::lowerKillInstrs(bool IsWQM) {
if (SplitPoint)
splitBlock(MBB, SplitPoint);
}
return !KillInstrs.empty();
}

void SIWholeQuadMode::lowerInitExec(MachineInstr &MI) {
Expand Down Expand Up @@ -1602,7 +1606,7 @@ void SIWholeQuadMode::lowerInitExec(MachineInstr &MI) {
/// Lower INIT_EXEC instructions. Return a suitable insert point in \p Entry
/// for instructions that depend on EXEC.
MachineBasicBlock::iterator
SIWholeQuadMode::lowerInitExecInstrs(MachineBasicBlock &Entry) {
SIWholeQuadMode::lowerInitExecInstrs(MachineBasicBlock &Entry, bool &Changed) {
MachineBasicBlock::iterator InsertPt = Entry.getFirstNonPHI();

for (MachineInstr *MI : InitExecInstrs) {
Expand All @@ -1613,6 +1617,7 @@ SIWholeQuadMode::lowerInitExecInstrs(MachineBasicBlock &Entry) {
InsertPt = std::next(MI->getIterator());

lowerInitExec(*MI);
Changed = true;
}

return InsertPt;
Expand Down Expand Up @@ -1666,20 +1671,12 @@ bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) {

const char GlobalFlags = analyzeFunction(MF);
const bool NeedsLiveMask = !(KillInstrs.empty() && LiveMaskQueries.empty());
bool Changed = false;

LiveMaskReg = Exec;

MachineBasicBlock &Entry = MF.front();
MachineBasicBlock::iterator EntryMI = lowerInitExecInstrs(Entry);

// Shader is simple does not need any state changes or any complex lowering
if (!(GlobalFlags & (StateWQM | StateStrict)) && LowerToCopyInstrs.empty() &&
LowerToMovInstrs.empty() && KillInstrs.empty()) {
lowerLiveMaskQueries();
if (!InitExecInstrs.empty())
LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
return !InitExecInstrs.empty() || !LiveMaskQueries.empty();
}
MachineBasicBlock::iterator EntryMI = lowerInitExecInstrs(Entry, Changed);

// Store a copy of the original live mask when required
if (NeedsLiveMask || (GlobalFlags & StateWQM)) {
Expand All @@ -1688,25 +1685,32 @@ bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) {
BuildMI(Entry, EntryMI, DebugLoc(), TII->get(AMDGPU::COPY), LiveMaskReg)
.addReg(Exec);
LIS->InsertMachineInstrInMaps(*MI);
Changed = true;
}

LLVM_DEBUG(printInfo());

lowerLiveMaskQueries();
lowerCopyInstrs();
Changed |= lowerLiveMaskQueries();
Changed |= lowerCopyInstrs();

// Shader only needs WQM
if (GlobalFlags == StateWQM) {
if (!(GlobalFlags & ~StateExact)) {
// No wave mode execution
Changed |= lowerKillInstrs(false);
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Before this patch we never called lowerKillInstrs(false). Was that a bug?

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No, it wasn't necessary.
We ran the whole lowering for an Exact shader with kills.
In the whole lower lowerBlock performs the same function as lowerKillInstrs.

} else if (GlobalFlags == StateWQM) {
// Shader only needs WQM
auto MI = BuildMI(Entry, EntryMI, DebugLoc(), TII->get(WQMOpc), Exec)
.addReg(Exec);
LIS->InsertMachineInstrInMaps(*MI);
lowerKillInstrs(true);
Changed = true;
} else {
// Wave mode switching requires full lowering pass.
for (auto BII : Blocks)
processBlock(*BII.first, BII.first == &Entry);
// Lowering blocks causes block splitting so perform as a second pass.
for (auto BII : Blocks)
lowerBlock(*BII.first);
Changed = true;
}

// Compute live range for live mask
Expand All @@ -1722,5 +1726,5 @@ bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) {
if (!KillInstrs.empty() || !InitExecInstrs.empty())
LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);

return true;
return Changed;
}
22 changes: 14 additions & 8 deletions llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,8 @@ declare void @llvm.amdgcn.raw.ptr.buffer.store.f32(float, ptr addrspace(8), i32,
define amdgpu_ps void @add_i32_constant(ptr addrspace(8) inreg %out, ptr addrspace(8) inreg %inout) {
; GFX7-LABEL: add_i32_constant:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], exec
; GFX7-NEXT: s_mov_b64 s[8:9], exec
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; GFX7-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX7-NEXT: ; implicit-def: $vgpr0
; GFX7-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX7-NEXT: s_cbranch_execz .LBB0_4
Expand Down Expand Up @@ -51,7 +52,8 @@ define amdgpu_ps void @add_i32_constant(ptr addrspace(8) inreg %out, ptr addrspa
;
; GFX89-LABEL: add_i32_constant:
; GFX89: ; %bb.0: ; %entry
; GFX89-NEXT: s_mov_b64 s[10:11], exec
; GFX89-NEXT: s_mov_b64 s[8:9], exec
; GFX89-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX89-NEXT: ; implicit-def: $vgpr0
; GFX89-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX89-NEXT: s_cbranch_execz .LBB0_4
Expand Down Expand Up @@ -86,8 +88,9 @@ define amdgpu_ps void @add_i32_constant(ptr addrspace(8) inreg %out, ptr addrspa
;
; GFX1064-LABEL: add_i32_constant:
; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[10:11], exec
; GFX1064-NEXT: s_mov_b64 s[8:9], exec
; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX1064-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX1064-NEXT: s_cbranch_execz .LBB0_4
; GFX1064-NEXT: ; %bb.1:
Expand Down Expand Up @@ -122,8 +125,9 @@ define amdgpu_ps void @add_i32_constant(ptr addrspace(8) inreg %out, ptr addrspa
;
; GFX1032-LABEL: add_i32_constant:
; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_mov_b32 s9, exec_lo
; GFX1032-NEXT: s_mov_b32 s8, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_mov_b32 s9, s8
; GFX1032-NEXT: s_and_saveexec_b32 s8, s9
; GFX1032-NEXT: s_cbranch_execz .LBB0_4
; GFX1032-NEXT: ; %bb.1:
Expand Down Expand Up @@ -157,9 +161,10 @@ define amdgpu_ps void @add_i32_constant(ptr addrspace(8) inreg %out, ptr addrspa
;
; GFX1164-LABEL: add_i32_constant:
; GFX1164: ; %bb.0: ; %entry
; GFX1164-NEXT: s_mov_b64 s[10:11], exec
; GFX1164-NEXT: s_mov_b64 s[8:9], exec
; GFX1164-NEXT: ; implicit-def: $vgpr0
; GFX1164-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1164-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX1164-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX1164-NEXT: s_cbranch_execz .LBB0_4
; GFX1164-NEXT: ; %bb.1:
Expand Down Expand Up @@ -199,9 +204,10 @@ define amdgpu_ps void @add_i32_constant(ptr addrspace(8) inreg %out, ptr addrspa
;
; GFX1132-LABEL: add_i32_constant:
; GFX1132: ; %bb.0: ; %entry
; GFX1132-NEXT: s_mov_b32 s9, exec_lo
; GFX1132-NEXT: s_mov_b32 s8, exec_lo
; GFX1132-NEXT: ; implicit-def: $vgpr0
; GFX1132-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1132-NEXT: s_mov_b32 s9, s8
; GFX1132-NEXT: s_and_saveexec_b32 s8, s9
; GFX1132-NEXT: s_cbranch_execz .LBB0_4
; GFX1132-NEXT: ; %bb.1:
Expand Down
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