[AArch64] Take cmn folding of the right-hand side into account when folding #97773

AreaZR · 2024-07-04T23:14:28Z

Turning a cmp into cmn saves an extra mov and negate instruction, so take that into account when choosing when to flip the compare operands.

llvmbot · 2024-07-04T23:15:00Z

@llvm/pr-subscribers-backend-aarch64

Author: AtariDreams (AtariDreams)

Changes

Turning a cmp into cmn saves an extra mov and negate instruction, so take that into account when choosing when to flip the compare operands.

Full diff: https://github.com/llvm/llvm-project/pull/97773.diff

3 Files Affected:

(modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+9-4)
(modified) llvm/test/CodeGen/AArch64/cmp-to-cmn.ll (+177-136)
(modified) llvm/test/CodeGen/AArch64/typepromotion-overflow.ll (+8-8)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e0c3cc5eddb82..84d57cbb994e2 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3876,10 +3876,15 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
   //    cmp     w13, w12
   // can be turned into:
   //    cmp     w12, w11, lsl #1
-  if (!isa<ConstantSDNode>(RHS) || !isLegalArithImmed(RHS->getAsZExtVal())) {
-    SDValue TheLHS = isCMN(LHS, CC) ? LHS.getOperand(1) : LHS;
-
-    if (getCmpOperandFoldingProfit(TheLHS) > getCmpOperandFoldingProfit(RHS)) {
+  if (!isa<ConstantSDNode>(RHS) ||
+      !isLegalArithImmed(RHS->getAsAPIntVal().abs().getZExtValue())) {
+    bool LHSIsCMN = isCMN(LHS, CC);
+    bool RHSIsCMN = isCMN(RHS, CC);
+    SDValue TheLHS = LHSIsCMN ? LHS.getOperand(1) : LHS;
+    SDValue TheRHS = RHSIsCMN ? RHS.getOperand(1) : RHS;
+
+    if (getCmpOperandFoldingProfit(TheLHS) + (LHSIsCMN ? 1 : 0) >
+        getCmpOperandFoldingProfit(TheRHS) + (RHSIsCMN ? 1 : 0)) {
       std::swap(LHS, RHS);
       CC = ISD::getSetCCSwappedOperands(CC);
     }
diff --git a/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll b/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
index 6da98142573f6..1cc194e77b94b 100644
--- a/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
+++ b/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
@@ -1,12 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "arm64"
 
 define i1 @test_EQ_IllEbT(i64 %a, i64 %b) {
-; CHECK-LABEL: test_EQ_IllEbT
-; CHECK:      cmn	x1, x0
-; CHECK-NEXT: cset	w0, eq
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_EQ_IllEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn x0, x1
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %add = sub i64 0, %b
   %cmp = icmp eq i64 %add, %a
@@ -14,10 +16,11 @@ entry:
 }
 
 define i1 @test_EQ_IliEbT(i64 %a, i32 %b) {
-; CHECK-LABEL: test_EQ_IliEbT
-; CHECK:      cmn	x0, w1, sxtw
-; CHECK-NEXT: cset	w0, eq
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_EQ_IliEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn x0, w1, sxtw
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i32 %b to i64
   %add = sub i64 0, %a
@@ -26,10 +29,12 @@ entry:
 }
 
 define i1 @test_EQ_IlsEbT(i64 %a, i16 %b) {
-; CHECK-LABEL: test_EQ_IlsEbT
-; CHECK:      cmn	x0, w1, sxth
-; CHECK-NEXT: cset	w0, eq
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_EQ_IlsEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT:    cmn x0, w1, sxth
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %b to i64
   %add = sub i64 0, %a
@@ -38,10 +43,12 @@ entry:
 }
 
 define i1 @test_EQ_IlcEbT(i64 %a, i8 %b) {
-; CHECK-LABEL: test_EQ_IlcEbT
-; CHECK: 	cmn	x0, w1, uxtb
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_EQ_IlcEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT:    cmn x0, w1, uxtb
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %b to i64
   %add = sub i64 0, %a
@@ -50,10 +57,11 @@ entry:
 }
 
 define i1 @test_EQ_IilEbT(i32 %a, i64 %b) {
-; CHECK-LABEL: test_EQ_IilEbT
-; CHECK: 	cmn	x1, w0, sxtw
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_EQ_IilEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn x1, w0, sxtw
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i32 %a to i64
   %add = sub i64 0, %b
@@ -62,10 +70,11 @@ entry:
 }
 
 define i1 @test_EQ_IiiEbT(i32 %a, i32 %b) {
-; CHECK-LABEL: test_EQ_IiiEbT
-; CHECK: 	cmn	w1, w0
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_EQ_IiiEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, w1
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %add = sub i32 0, %b
   %cmp = icmp eq i32 %add, %a
@@ -73,10 +82,11 @@ entry:
 }
 
 define i1 @test_EQ_IisEbT(i32 %a, i16 %b) {
-; CHECK-LABEL: test_EQ_IisEbT
-; CHECK: 	cmn	w0, w1, sxth
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_EQ_IisEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, w1, sxth
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %b to i32
   %add = sub i32 0, %a
@@ -85,10 +95,11 @@ entry:
 }
 
 define i1 @test_EQ_IicEbT(i32 %a, i8 %b) {
-; CHECK-LABEL: test_EQ_IicEbT
-; CHECK: 	cmn	w0, w1, uxtb
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_EQ_IicEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, w1, uxtb
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %b to i32
   %add = sub i32 0, %a
@@ -97,10 +108,12 @@ entry:
 }
 
 define i1 @test_EQ_IslEbT(i16 %a, i64 %b) {
-; CHECK-LABEL: test_EQ_IslEbT
-; CHECK: 	cmn	x1, w0, sxth
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_EQ_IslEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    cmn x1, w0, sxth
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %a to i64
   %add = sub i64 0, %b
@@ -109,10 +122,11 @@ entry:
 }
 
 define i1 @test_EQ_IsiEbT(i16 %a, i32 %b) {
-; CHECK-LABEL: test_EQ_IsiEbT
-; CHECK: 	cmn	w1, w0, sxth
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_EQ_IsiEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w1, w0, sxth
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %a to i32
   %add = sub i32 0, %b
@@ -121,11 +135,12 @@ entry:
 }
 
 define i1 @test_EQ_IssEbT(i16 %a, i16 %b) {
-; CHECK-LABEL: test_EQ_IssEbT
-; CHECK: 	sxth	w8, w1
-; CHECK-NEXT: 	cmn	w8, w0, sxth
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT:   ret
+; CHECK-LABEL: test_EQ_IssEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sxth w8, w0
+; CHECK-NEXT:    cmn w8, w1, sxth
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %a to i32
   %conv1 = sext i16 %b to i32
@@ -135,11 +150,12 @@ entry:
 }
 
 define i1 @test_EQ_IscEbT(i16 %a, i8 %b) {
-; CHECK-LABEL: test_EQ_IscEbT
-; CHECK: 	and	w8, w1, #0xff
-; CHECK-NEXT: 	cmn	w8, w0, sxth
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT:   ret
+; CHECK-LABEL: test_EQ_IscEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sxth w8, w0
+; CHECK-NEXT:    cmn w8, w1, uxtb
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %a to i32
   %conv1 = zext i8 %b to i32
@@ -149,10 +165,12 @@ entry:
 }
 
 define i1 @test_EQ_IclEbT(i8 %a, i64 %b) {
-; CHECK-LABEL: test_EQ_IclEbT
-; CHECK:      	cmn	x1, w0, uxtb
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_EQ_IclEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    cmn x1, w0, uxtb
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %a to i64
   %add = sub i64 0, %b
@@ -161,10 +179,11 @@ entry:
 }
 
 define i1 @test_EQ_IciEbT(i8 %a, i32 %b) {
-; CHECK-LABEL: test_EQ_IciEbT
-; CHECK:      	cmn	w1, w0, uxtb
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_EQ_IciEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w1, w0, uxtb
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %a to i32
   %add = sub i32 0, %b
@@ -173,11 +192,12 @@ entry:
 }
 
 define i1 @test_EQ_IcsEbT(i8 %a, i16 %b) {
-; CHECK-LABEL: test_EQ_IcsEbT
-; CHECK:      	sxth	w8, w1
-; CHECK-NEXT: 	cmn	w8, w0, uxtb
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT:	ret
+; CHECK-LABEL: test_EQ_IcsEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    cmn w8, w1, sxth
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %a to i32
   %conv1 = sext i16 %b to i32
@@ -187,11 +207,12 @@ entry:
 }
 
 define i1 @test_EQ_IccEbT(i8 %a, i8 %b) {
-; CHECK-LABEL: test_EQ_IccEbT
-; CHECK:      	and	w8, w1, #0xff
-; CHECK-NEXT: 	cmn	w8, w0, uxtb
-; CHECK-NEXT: 	cset	w0, eq
-; CHECK-NEXT:	ret
+; CHECK-LABEL: test_EQ_IccEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    cmn w8, w1, uxtb
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %a to i32
   %conv1 = zext i8 %b to i32
@@ -201,10 +222,11 @@ entry:
 }
 
 define i1 @test_NE_IllEbT(i64 %a, i64 %b) {
-; CHECK-LABEL: test_NE_IllEbT
-; CHECK:      	cmn	x1, x0
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IllEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn x0, x1
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %add = sub i64 0, %b
   %cmp = icmp ne i64 %add, %a
@@ -212,10 +234,11 @@ entry:
 }
 
 define i1 @test_NE_IliEbT(i64 %a, i32 %b) {
-; CHECK-LABEL: test_NE_IliEbT
-; CHECK:      	cmn	x0, w1, sxtw
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IliEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn x0, w1, sxtw
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i32 %b to i64
   %add = sub i64 0, %a
@@ -224,10 +247,12 @@ entry:
 }
 
 define i1 @test_NE_IlsEbT(i64 %a, i16 %b) {
-; CHECK-LABEL: test_NE_IlsEbT
-; CHECK:      	cmn	x0, w1, sxth
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IlsEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT:    cmn x0, w1, sxth
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %b to i64
   %add = sub i64 0, %a
@@ -236,10 +261,12 @@ entry:
 }
 
 define i1 @test_NE_IlcEbT(i64 %a, i8 %b) {
-; CHECK-LABEL: test_NE_IlcEbT
-; CHECK:      	cmn	x0, w1, uxtb
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IlcEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT:    cmn x0, w1, uxtb
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %b to i64
   %add = sub i64 0, %a
@@ -248,10 +275,11 @@ entry:
 }
 
 define i1 @test_NE_IilEbT(i32 %a, i64 %b) {
-; CHECK-LABEL: test_NE_IilEbT
-; CHECK:      	cmn	x1, w0, sxtw
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IilEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn x1, w0, sxtw
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i32 %a to i64
   %add = sub i64 0, %b
@@ -260,10 +288,11 @@ entry:
 }
 
 define i1 @test_NE_IiiEbT(i32 %a, i32 %b) {
-; CHECK-LABEL: test_NE_IiiEbT
-; CHECK:      	cmn	w1, w0
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IiiEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, w1
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %add = sub i32 0, %b
   %cmp = icmp ne i32 %add, %a
@@ -271,10 +300,11 @@ entry:
 }
 
 define i1 @test_NE_IisEbT(i32 %a, i16 %b) {
-; CHECK-LABEL: test_NE_IisEbT
-; CHECK:      	cmn	w0, w1, sxth
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IisEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, w1, sxth
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %b to i32
   %add = sub i32 0, %a
@@ -283,10 +313,11 @@ entry:
 }
 
 define i1 @test_NE_IicEbT(i32 %a, i8 %b) {
-; CHECK-LABEL: test_NE_IicEbT
-; CHECK:      	cmn	w0, w1, uxtb
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IicEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, w1, uxtb
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %b to i32
   %add = sub i32 0, %a
@@ -295,10 +326,12 @@ entry:
 }
 
 define i1 @test_NE_IslEbT(i16 %a, i64 %b) {
-; CHECK-LABEL: test_NE_IslEbT
-; CHECK:      	cmn	x1, w0, sxth
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IslEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    cmn x1, w0, sxth
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %a to i64
   %add = sub i64 0, %b
@@ -307,10 +340,11 @@ entry:
 }
 
 define i1 @test_NE_IsiEbT(i16 %a, i32 %b) {
-; CHECK-LABEL: test_NE_IsiEbT
-; CHECK:      	cmn	w1, w0, sxth
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IsiEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w1, w0, sxth
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %a to i32
   %add = sub i32 0, %b
@@ -319,11 +353,12 @@ entry:
 }
 
 define i1 @test_NE_IssEbT(i16 %a, i16 %b) {
-; CHECK-LABEL:test_NE_IssEbT
-; CHECK:      	sxth	w8, w1
-; CHECK-NEXT: 	cmn	w8, w0, sxth
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT:	ret
+; CHECK-LABEL: test_NE_IssEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sxth w8, w0
+; CHECK-NEXT:    cmn w8, w1, sxth
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %a to i32
   %conv1 = sext i16 %b to i32
@@ -333,11 +368,12 @@ entry:
 }
 
 define i1 @test_NE_IscEbT(i16 %a, i8 %b) {
-; CHECK-LABEL:test_NE_IscEbT
-; CHECK:      	and	w8, w1, #0xff
-; CHECK-NEXT: 	cmn	w8, w0, sxth
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT:	ret
+; CHECK-LABEL: test_NE_IscEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sxth w8, w0
+; CHECK-NEXT:    cmn w8, w1, uxtb
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = sext i16 %a to i32
   %conv1 = zext i8 %b to i32
@@ -347,10 +383,12 @@ entry:
 }
 
 define i1 @test_NE_IclEbT(i8 %a, i64 %b) {
-; CHECK-LABEL:test_NE_IclEbT
-; CHECK:      	cmn	x1, w0, uxtb
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IclEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    cmn x1, w0, uxtb
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %a to i64
   %add = sub i64 0, %b
@@ -359,10 +397,11 @@ entry:
 }
 
 define i1 @test_NE_IciEbT(i8 %a, i32 %b) {
-; CHECK-LABEL:test_NE_IciEbT
-; CHECK:      	cmn	w1, w0, uxtb
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT: 	ret
+; CHECK-LABEL: test_NE_IciEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w1, w0, uxtb
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %a to i32
   %add = sub i32 0, %b
@@ -371,11 +410,12 @@ entry:
 }
 
 define i1 @test_NE_IcsEbT(i8 %a, i16 %b) {
-; CHECK-LABEL:test_NE_IcsEbT
-; CHECK:      	sxth	w8, w1
-; CHECK-NEXT: 	cmn	w8, w0, uxtb
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT:	ret
+; CHECK-LABEL: test_NE_IcsEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    cmn w8, w1, sxth
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %a to i32
   %conv1 = sext i16 %b to i32
@@ -385,11 +425,12 @@ entry:
 }
 
 define i1 @test_NE_IccEbT(i8 %a, i8 %b) {
-; CHECK-LABEL:test_NE_IccEbT
-; CHECK:      	and	w8, w1, #0xff
-; CHECK-NEXT: 	cmn	w8, w0, uxtb
-; CHECK-NEXT: 	cset	w0, ne
-; CHECK-NEXT:	ret
+; CHECK-LABEL: test_NE_IccEbT:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    cmn w8, w1, uxtb
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
 entry:
   %conv = zext i8 %a to i32
   %conv1 = zext i8 %b to i32
diff --git a/llvm/test/CodeGen/AArch64/typepromotion-overflow.ll b/llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
index 39edc03ced442..2451ea478ed71 100644
--- a/llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
+++ b/llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
@@ -107,11 +107,11 @@ define i32 @overflow_add_const_limit(i8 zeroext %a, i8 zeroext %b) {
 define i32 @overflow_add_positive_const_limit(i8 zeroext %a) {
 ; CHECK-LABEL: overflow_add_positive_const_limit:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-1 // =0xffffffff
-; CHECK-NEXT:    mov w9, #8 // =0x8
-; CHECK-NEXT:    cmp w8, w0, sxtb
+; CHECK-NEXT:    sxtb w9, w0
 ; CHECK-NEXT:    mov w8, #16 // =0x10
-; CHECK-NEXT:    csel w0, w9, w8, gt
+; CHECK-NEXT:    cmn w9, #1
+; CHECK-NEXT:    mov w9, #8 // =0x8
+; CHECK-NEXT:    csel w0, w9, w8, lt
 ; CHECK-NEXT:    ret
   %cmp = icmp slt i8 %a, -1
   %res = select i1 %cmp, i32 8, i32 16
@@ -162,11 +162,11 @@ define i32 @safe_add_underflow_neg(i8 zeroext %a) {
 define i32 @overflow_sub_negative_const_limit(i8 zeroext %a) {
 ; CHECK-LABEL: overflow_sub_negative_const_limit:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-1 // =0xffffffff
-; CHECK-NEXT:    mov w9, #8 // =0x8
-; CHECK-NEXT:    cmp w8, w0, sxtb
+; CHECK-NEXT:    sxtb w9, w0
 ; CHECK-NEXT:    mov w8, #16 // =0x10
-; CHECK-NEXT:    csel w0, w9, w8, gt
+; CHECK-NEXT:    cmn w9, #1
+; CHECK-NEXT:    mov w9, #8 // =0x8
+; CHECK-NEXT:    csel w0, w9, w8, lt
 ; CHECK-NEXT:    ret
   %cmp = icmp slt i8 %a, -1
   %res = select i1 %cmp, i32 8, i32 16

…olding Turning a cmp into cmn saves an extra mov and negate instruction, so take that into account when choosing when to flip the compare operands. Also do not consider right-hand operands whose absolute value can be encoded into a cmn.

llvmbot added the backend:AArch64 label Jul 4, 2024

AreaZR force-pushed the sides branch from 65fec66 to 213d1cb Compare July 4, 2024 23:15

AreaZR mentioned this pull request Jul 4, 2024

[AArch64] Take cmn into account when adjusting compare constants #97774

Closed

AreaZR force-pushed the sides branch from 213d1cb to 2a31ee0 Compare July 4, 2024 23:38

AreaZR closed this Jul 5, 2024

AreaZR deleted the sides branch July 5, 2024 00:27

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

[AArch64] Take cmn folding of the right-hand side into account when folding #97773

[AArch64] Take cmn folding of the right-hand side into account when folding #97773

AreaZR commented Jul 4, 2024

llvmbot commented Jul 4, 2024

[AArch64] Take cmn folding of the right-hand side into account when folding #97773

[AArch64] Take cmn folding of the right-hand side into account when folding #97773

Conversation

AreaZR commented Jul 4, 2024

llvmbot commented Jul 4, 2024