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[AMDGPU] Fix kernarg preloading crash with some types and alignments #91625

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May 20, 2024
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20 changes: 14 additions & 6 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2976,12 +2976,20 @@ SDValue SITargetLowering::LowerFormalArguments(
DL, Elts);
}

SDValue CMemVT;
if (VT.isScalarInteger() && VT.bitsLT(NewArg.getSimpleValueType()))
CMemVT = DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewArg);
else
CMemVT = DAG.getBitcast(MemVT, NewArg);
NewArg = convertArgType(DAG, VT, MemVT, DL, CMemVT,
// If the argument was preloaded to multiple consecutive 32-bit
// registers because of misalignment between addressable SGPR tuples
// and the argument size, we can still assume that because of kernarg
// segment alignment restrictions that NewArg's size is the same as
// MemVT and just do a bitcast. If MemVT is less than 32-bits we add a
// truncate since we cannot preload to less than a single SGPR and the
// MemVT may be smaller.
EVT MemVTInt =
EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
if (MemVT.bitsLT(NewArg.getSimpleValueType()))
NewArg = DAG.getNode(ISD::TRUNCATE, DL, MemVTInt, NewArg);

NewArg = DAG.getBitcast(MemVT, NewArg);
NewArg = convertArgType(DAG, VT, MemVT, DL, NewArg,
Ins[i].Flags.isSExt(), &Ins[i]);
NewArg = DAG.getMergeValues({NewArg, Chain}, DL);
}
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