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[X86] Recognize POP/ADD/SUB modifying rsp in getSPAdjust. #114265

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[X86] Recognize POP/ADD/SUB modifying rsp in getSPAdjust. #114265

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31 changes: 29 additions & 2 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -452,10 +452,13 @@ int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
return -(I->getOperand(1).getImm());
}

// Currently handle only PUSHes we can reasonably expect to see
// in call sequences
// Handle other opcodes we reasonably expect to see in call
// sequences. Note this may include spill/restore of FP/BP.
switch (MI.getOpcode()) {
default:
assert(!(MI.modifiesRegister(X86::RSP, &RI) ||
MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP)) &&
"Unhandled opcode in getSPAdjust");
return 0;
case X86::PUSH32r:
case X86::PUSH32rmm:
Expand All @@ -467,6 +470,30 @@ int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
case X86::PUSH64rmr:
case X86::PUSH64i32:
return 8;
case X86::POP32r:
case X86::POP32rmm:
case X86::POP32rmr:
return -4;
case X86::POP64r:
case X86::POP64rmm:
case X86::POP64rmr:
return -8;
// FIXME: (implement and) use isAddImmediate in the
// default case instead of the following ADD/SUB cases.
case X86::ADD32ri:
case X86::ADD32ri8:
case X86::ADD64ri32:
if (MI.getOperand(0).getReg() == X86::RSP &&
MI.getOperand(1).getReg() == X86::RSP)
return -MI.getOperand(2).getImm();
return 0;
case X86::SUB32ri:
case X86::SUB32ri8:
case X86::SUB64ri32:
if (MI.getOperand(0).getReg() == X86::RSP &&
MI.getOperand(1).getReg() == X86::RSP)
return MI.getOperand(2).getImm();
return 0;
}
}

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