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[RISCV] Cost ordered bf16/f16 w/ zvfhmin reductions as invalid #114250

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[RISCV] Cost ordered bf16/f16 w/ zvfhmin reductions as invalid #114250

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[RISCV] Cost ordered bf16/f16 w/ zvfhmin reductions as invalid
lukel97 Oct 30, 2024
52be2b5
Check legalized type
lukel97 Oct 30, 2024
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13 changes: 8 additions & 5 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1524,6 +1524,14 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
return BaseT::getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);

std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
// We can't promote f16/bf16 fadd reductions.
if (ISD == ISD::FADD && ((LT.second.getVectorElementType() == MVT::f16 &&
!ST->hasVInstructionsF16()) ||
LT.second.getVectorElementType() == MVT::bf16)) {
// We can't lower scalable vectors, but we can expand fixed vectors.
return BaseT::getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
}

SmallVector<unsigned, 3> Opcodes;
Type *ElementTy = Ty->getElementType();
if (ElementTy->isIntegerTy(1)) {
Expand Down Expand Up @@ -1578,11 +1586,6 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
Opcodes = {RISCV::VMV_S_X, RISCV::VREDAND_VS, RISCV::VMV_X_S};
break;
case ISD::FADD:
// We can't promote f16/bf16 fadd reductions.
if ((LT.second.getVectorElementType() == MVT::f16 &&
!ST->hasVInstructionsF16()) ||
LT.second.getVectorElementType() == MVT::bf16)
return InstructionCost::getInvalid();
SplitOp = RISCV::VFADD_VV;
Opcodes = {RISCV::VFMV_S_F, RISCV::VFREDUSUM_VS, RISCV::VFMV_F_S};
break;
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