Commits on Oct 30, 2024

1. AMDGPU/GlobalISel: Add skeletons for new register bank select passes …

   New register bank select for AMDGPU will be split in two passes:
   - AMDGPURegBankSelect: select banks based on machine uniformity analysis
   - AMDGPURegBankLegalize: lower instructions that can't be inst-selected
     with register banks assigned by AMDGPURegBankSelect.
   AMDGPURegBankLegalize is similar to legalizer but with context of
   uniformity analysis. Does not change already assigned banks.
   Main goal of AMDGPURegBankLegalize is to provide high level table-like
   overview of how to lower generic instructions based on available target
   features and uniformity info (uniform vs divergent).
   See RegBankLegalizeRules.
   
   Summary of new features:
   At the moment register bank select assigns register bank to output
   register using simple algorithm:
   - one of the inputs is vgpr output is vgpr
   - all inputs are sgpr output is sgpr.
   When function does not contain divergent control flow propagating
   register banks like this works. In general, first point is still correct
   but second is not when function contains divergent control flow.
   Examples:
   - Phi with uniform inputs that go through divergent branch
   - Instruction with temporal divergent use.
   To fix this AMDGPURegBankSelect will use machine uniformity analysis
   to assign vgpr to each divergent and sgpr to each uniform instruction.
   But some instructions are only available on VALU (for example floating
   point instructions before gfx1150) and we need to assign vgpr to them.
   Since we are no longer propagating register banks we need to ensure that
   uniform instructions get their inputs in sgpr in some way.
   In AMDGPURegBankLegalize uniform instructions that are only available on
   VALU will be reassigned to vgpr on all operands and read-any-lane vgpr
   output to original sgpr output.

   

   petar-avramovic committed Oct 30, 2024
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