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Change-Id: Ifc338ac65db118812affc782e08d32ca6a27516e
llvm · Jul 2, 2024 · c21160f · c21160f
1 parent 6d60b39
commit c21160f
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Showing 2 changed files with 9 additions and 4 deletions.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -306,16 +306,21 @@ bool GCNTTIImpl::hasBranchDivergence(const Function *F) const {
   return !F || !ST->isSingleLaneExecution(*F);
 }
 
-unsigned GCNTTIImpl::getNumberOfParts(Type *Tp) const {
+unsigned GCNTTIImpl::getNumberOfParts(Type *Tp) {
+  // For certain 8 bit ops, we can pack a v4i8 into a single part
+  // (e.g. v4i8 shufflevectors -> v_perm v4i8, v4i8). Thus, we
+  // do not limit the numberOfParts for 8 bit vectors to the
+  // legalization costs of such. It is left up to other target
+  // queries (e.g. get*InstrCost) to decide the proper handling
+  // of 8 bit vectors.
   if (FixedVectorType *VTy = dyn_cast<FixedVectorType>(Tp)) {
     if (DL.getTypeSizeInBits(VTy->getElementType()) == 8) {
       unsigned ElCount = VTy->getElementCount().getFixedValue();
       return ElCount / 4;
     }
   }
 
-  std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Tp);
-  return LT.first.isValid() ? *LT.first.getValue() : 0;
+  return BaseT::getNumberOfParts(Tp);
 }
 
 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const {

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -117,7 +117,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
     return TTI::PSK_FastHardware;
   }
 
-  unsigned getNumberOfParts(Type *Tp) const;
+  unsigned getNumberOfParts(Type *Tp);
   unsigned getNumberOfRegisters(unsigned RCID) const;
   TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
   unsigned getMinVectorRegisterBitWidth() const;