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[RISCV] update tests
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@dlav-sc
dlav-sc committed Oct 2, 2024
1 parent b51b26e commit a58cf3f
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Showing 7 changed files with 21 additions and 72 deletions.
20 changes: 4 additions & 16 deletions llvm/test/CodeGen/RISCV/branch-relaxation.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -824,10 +824,7 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
; CHECK-RV32-NEXT: #APP
; CHECK-RV32-NEXT: # reg use t6
; CHECK-RV32-NEXT: #NO_APP
; CHECK-RV32-NEXT: lui a0, 2
; CHECK-RV32-NEXT: sub sp, s0, a0
; CHECK-RV32-NEXT: addi a0, a0, -2032
; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: addi sp, s0, -2032
; CHECK-RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -1073,10 +1070,7 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
; CHECK-RV64-NEXT: #APP
; CHECK-RV64-NEXT: # reg use t6
; CHECK-RV64-NEXT: #NO_APP
; CHECK-RV64-NEXT: lui a0, 2
; CHECK-RV64-NEXT: sub sp, s0, a0
; CHECK-RV64-NEXT: addiw a0, a0, -2032
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: addi sp, s0, -2032
; CHECK-RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -2323,10 +2317,7 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-RV32-NEXT: #APP
; CHECK-RV32-NEXT: # reg use t6
; CHECK-RV32-NEXT: #NO_APP
; CHECK-RV32-NEXT: lui a0, 2
; CHECK-RV32-NEXT: sub sp, s0, a0
; CHECK-RV32-NEXT: addi a0, a0, -2032
; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: addi sp, s0, -2032
; CHECK-RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -2560,10 +2551,7 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-RV64-NEXT: #APP
; CHECK-RV64-NEXT: # reg use t6
; CHECK-RV64-NEXT: #NO_APP
; CHECK-RV64-NEXT: lui a0, 2
; CHECK-RV64-NEXT: sub sp, s0, a0
; CHECK-RV64-NEXT: addiw a0, a0, -2032
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: addi sp, s0, -2032
; CHECK-RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload
Expand Down
5 changes: 1 addition & 4 deletions llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -41,10 +41,7 @@
; CHECK-NEXT: sd a0, -8(a1)
; CHECK-NEXT: ld a1, 0(sp)
; CHECK-NEXT: call foo
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: sub sp, s0, a0
; CHECK-NEXT: addiw a0, a0, -2032
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, s0, -2032
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 2032
Expand Down
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -46,9 +46,7 @@ body: |
; CHECK-NEXT: $x10 = ADDI killed $x10, -2048
; CHECK-NEXT: $x10 = ADDI killed $x10, -224
; CHECK-NEXT: VS1R_V killed renamable $v8, killed renamable $x10
; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2048
; CHECK-NEXT: $x2 = frame-destroy ADDI killed $x2, -224
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240
; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2032
; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3)
; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032
Expand Down
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -109,9 +109,7 @@ define riscv_vector_cc void @local_stack_allocation_frame_pointer() "frame-point
; SPILL-O2-NEXT: addi sp, sp, -480
; SPILL-O2-NEXT: lbu a0, -1912(s0)
; SPILL-O2-NEXT: sb a0, -1912(s0)
; SPILL-O2-NEXT: addi sp, s0, -2048
; SPILL-O2-NEXT: addi sp, sp, -464
; SPILL-O2-NEXT: addi sp, sp, 480
; SPILL-O2-NEXT: addi sp, s0, -2032
; SPILL-O2-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; SPILL-O2-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; SPILL-O2-NEXT: addi sp, sp, 2032
Expand Down
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -150,9 +150,7 @@ body: |
; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2048
; CHECK-NEXT: $x2 = frame-destroy ADDI killed $x2, -256
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 272
; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2032
; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3)
; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
; CHECK-NEXT: $x18 = LD $x2, 2008 :: (load (s64) from %stack.5)
Expand Down
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,7 @@
; CHECK-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: ld a0, 8(sp)
; CHECK-NEXT: call spillslot
; CHECK-NEXT: addi sp, s0, -2048
; CHECK-NEXT: addi sp, sp, -256
; CHECK-NEXT: addi sp, sp, 272
; CHECK-NEXT: addi sp, s0, -2032
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 2032
Expand Down
52 changes: 12 additions & 40 deletions llvm/test/CodeGen/RISCV/stack-realignment.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -815,8 +815,7 @@ define void @caller1024() {
; RV32I-NEXT: andi sp, sp, -1024
; RV32I-NEXT: addi a0, sp, 1024
; RV32I-NEXT: call callee
; RV32I-NEXT: addi sp, s0, -2048
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: addi sp, s0, -2032
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032
Expand All @@ -836,8 +835,7 @@ define void @caller1024() {
; RV32I-ILP32E-NEXT: andi sp, sp, -1024
; RV32I-ILP32E-NEXT: addi a0, sp, 1024
; RV32I-ILP32E-NEXT: call callee
; RV32I-ILP32E-NEXT: addi sp, s0, -2048
; RV32I-ILP32E-NEXT: addi sp, sp, 4
; RV32I-ILP32E-NEXT: addi sp, s0, -2044
; RV32I-ILP32E-NEXT: lw ra, 2040(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: lw s0, 2036(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: addi sp, sp, 2044
Expand All @@ -857,8 +855,7 @@ define void @caller1024() {
; RV64I-NEXT: andi sp, sp, -1024
; RV64I-NEXT: addi a0, sp, 1024
; RV64I-NEXT: call callee
; RV64I-NEXT: addi sp, s0, -2048
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: addi sp, s0, -2032
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 2032
Expand All @@ -878,8 +875,7 @@ define void @caller1024() {
; RV64I-LP64E-NEXT: andi sp, sp, -1024
; RV64I-LP64E-NEXT: addi a0, sp, 1024
; RV64I-LP64E-NEXT: call callee
; RV64I-LP64E-NEXT: addi sp, s0, -2048
; RV64I-LP64E-NEXT: addi sp, sp, 8
; RV64I-LP64E-NEXT: addi sp, s0, -2040
; RV64I-LP64E-NEXT: ld ra, 2032(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: ld s0, 2024(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: addi sp, sp, 2040
Expand Down Expand Up @@ -959,10 +955,7 @@ define void @caller2048() {
; RV32I-NEXT: addi a0, sp, 2047
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: call callee
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: sub sp, s0, a0
; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: addi sp, s0, -2032
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032
Expand All @@ -984,10 +977,7 @@ define void @caller2048() {
; RV32I-ILP32E-NEXT: addi a0, sp, 2047
; RV32I-ILP32E-NEXT: addi a0, a0, 1
; RV32I-ILP32E-NEXT: call callee
; RV32I-ILP32E-NEXT: lui a0, 1
; RV32I-ILP32E-NEXT: sub sp, s0, a0
; RV32I-ILP32E-NEXT: addi sp, sp, 2044
; RV32I-ILP32E-NEXT: addi sp, sp, 8
; RV32I-ILP32E-NEXT: addi sp, s0, -2044
; RV32I-ILP32E-NEXT: lw ra, 2040(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: lw s0, 2036(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: addi sp, sp, 2044
Expand All @@ -1009,10 +999,7 @@ define void @caller2048() {
; RV64I-NEXT: addi a0, sp, 2047
; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: call callee
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: sub sp, s0, a0
; RV64I-NEXT: addi sp, sp, 2032
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: addi sp, s0, -2032
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 2032
Expand All @@ -1034,10 +1021,7 @@ define void @caller2048() {
; RV64I-LP64E-NEXT: addi a0, sp, 2047
; RV64I-LP64E-NEXT: addi a0, a0, 1
; RV64I-LP64E-NEXT: call callee
; RV64I-LP64E-NEXT: lui a0, 1
; RV64I-LP64E-NEXT: sub sp, s0, a0
; RV64I-LP64E-NEXT: addi sp, sp, 2040
; RV64I-LP64E-NEXT: addi sp, sp, 16
; RV64I-LP64E-NEXT: addi sp, s0, -2040
; RV64I-LP64E-NEXT: ld ra, 2032(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: ld s0, 2024(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: addi sp, sp, 2040
Expand Down Expand Up @@ -1119,10 +1103,7 @@ define void @caller4096() {
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: call callee
; RV32I-NEXT: lui a0, 2
; RV32I-NEXT: sub sp, s0, a0
; RV32I-NEXT: addi a0, a0, -2032
; RV32I-NEXT: add sp, sp, a0
; RV32I-NEXT: addi sp, s0, -2032
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032
Expand All @@ -1146,10 +1127,7 @@ define void @caller4096() {
; RV32I-ILP32E-NEXT: lui a0, 1
; RV32I-ILP32E-NEXT: add a0, sp, a0
; RV32I-ILP32E-NEXT: call callee
; RV32I-ILP32E-NEXT: lui a0, 2
; RV32I-ILP32E-NEXT: sub sp, s0, a0
; RV32I-ILP32E-NEXT: addi a0, a0, -2044
; RV32I-ILP32E-NEXT: add sp, sp, a0
; RV32I-ILP32E-NEXT: addi sp, s0, -2044
; RV32I-ILP32E-NEXT: lw ra, 2040(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: lw s0, 2036(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: addi sp, sp, 2044
Expand All @@ -1173,10 +1151,7 @@ define void @caller4096() {
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: add a0, sp, a0
; RV64I-NEXT: call callee
; RV64I-NEXT: lui a0, 2
; RV64I-NEXT: sub sp, s0, a0
; RV64I-NEXT: addiw a0, a0, -2032
; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: addi sp, s0, -2032
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 2032
Expand All @@ -1200,10 +1175,7 @@ define void @caller4096() {
; RV64I-LP64E-NEXT: lui a0, 1
; RV64I-LP64E-NEXT: add a0, sp, a0
; RV64I-LP64E-NEXT: call callee
; RV64I-LP64E-NEXT: lui a0, 2
; RV64I-LP64E-NEXT: sub sp, s0, a0
; RV64I-LP64E-NEXT: addiw a0, a0, -2040
; RV64I-LP64E-NEXT: add sp, sp, a0
; RV64I-LP64E-NEXT: addi sp, s0, -2040
; RV64I-LP64E-NEXT: ld ra, 2032(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: ld s0, 2024(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: addi sp, sp, 2040
Expand Down

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