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[CodeGen] Pre-commit tests (NFC)
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@AreaZR
AreaZR committed Jul 15, 2024
1 parent da286c8 commit 7ed4e9f
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55 changes: 55 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -269,3 +269,58 @@ define i32 @udiv_div_by_180(i32 %x)
%udiv = udiv i32 %truncate, 180
ret i32 %udiv
}

define i32 @udiv_div_by_180_exact(i32 %x)
; SDAG-LABEL: udiv_div_by_180_exact:
; SDAG: // %bb.0:
; SDAG-NEXT: lsr w8, w0, #2
; SDAG-NEXT: mov w9, #27671 // =0x6c17
; SDAG-NEXT: movk w9, #5825, lsl #16
; SDAG-NEXT: umull x8, w8, w9
; SDAG-NEXT: lsr x0, x8, #34
; SDAG-NEXT: // kill: def $w0 killed $w0 killed $x0
; SDAG-NEXT: ret
;
; GISEL-LABEL: udiv_div_by_180_exact:
; GISEL: // %bb.0:
; GISEL-NEXT: lsr w8, w0, #2
; GISEL-NEXT: mov w9, #27671 // =0x6c17
; GISEL-NEXT: movk w9, #5825, lsl #16
; GISEL-NEXT: umull x8, w8, w9
; GISEL-NEXT: lsr x8, x8, #32
; GISEL-NEXT: lsr w0, w8, #2
; GISEL-NEXT: ret
{
%udiv = udiv exact i32 %x, 180
ret i32 %udiv
}

define <4 x i32> @udiv_div_by_104_exact(<4 x i32> %x)
; SDAG-LABEL: udiv_div_by_104_exact:
; SDAG: // %bb.0:
; SDAG-NEXT: adrp x8, .LCPI8_0
; SDAG-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]
; SDAG-NEXT: adrp x8, .LCPI8_1
; SDAG-NEXT: umull2 v2.2d, v0.4s, v1.4s
; SDAG-NEXT: umull v0.2d, v0.2s, v1.2s
; SDAG-NEXT: ldr q1, [x8, :lo12:.LCPI8_1]
; SDAG-NEXT: uzp2 v0.4s, v0.4s, v2.4s
; SDAG-NEXT: ushl v0.4s, v0.4s, v1.4s
; SDAG-NEXT: ret
;
; GISEL-LABEL: udiv_div_by_104_exact:
; GISEL: // %bb.0:
; GISEL-NEXT: adrp x8, .LCPI8_1
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI8_1]
; GISEL-NEXT: adrp x8, .LCPI8_0
; GISEL-NEXT: umull2 v2.2d, v0.4s, v1.4s
; GISEL-NEXT: umull v0.2d, v0.2s, v1.2s
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]
; GISEL-NEXT: neg v1.4s, v1.4s
; GISEL-NEXT: uzp2 v0.4s, v0.4s, v2.4s
; GISEL-NEXT: ushl v0.4s, v0.4s, v1.4s
; GISEL-NEXT: ret
{
%udiv = udiv exact <4 x i32> %x, <i32 104, i32 72, i32 104, i32 72>
ret <4 x i32> %udiv
}
123 changes: 123 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -304,5 +304,128 @@ body: |
%10:_(<8 x s16>) = G_UDIV %0, %1
$q0 = COPY %10(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: udiv_exact
body: |
bb.1:
liveins: $w0
; CHECK-LABEL: name: udiv_exact
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1321528399
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[C]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UMULH]], [[C1]](s32)
; CHECK-NEXT: $w0 = COPY [[LSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = G_CONSTANT i32 104
%2:_(s32) = exact G_UDIV %0, %1
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: udiv_noexact
body: |
bb.1:
liveins: $w0
; CHECK-LABEL: name: udiv_noexact
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1321528399
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[C]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UMULH]], [[C1]](s32)
; CHECK-NEXT: $w0 = COPY [[LSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = G_CONSTANT i32 104
%2:_(s32) = G_UDIV %0, %1
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: udiv_exact_minsize
body: |
bb.1:
liveins: $w0
; CHECK-LABEL: name: udiv_exact_minsize
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1321528399
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[C]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UMULH]], [[C1]](s32)
; CHECK-NEXT: $w0 = COPY [[LSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = G_CONSTANT i32 104
%2:_(s32) = exact G_UDIV %0, %1
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: div_v4s32
body: |
bb.1:
liveins: $q0
; CHECK-LABEL: name: div_v4s32
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1321528399
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 954437177
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C2]](s32), [[C]](s32), [[C2]](s32)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C3]](s32), [[C1]](s32), [[C3]](s32)
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<4 x s32>) = G_UMULH [[COPY]], [[BUILD_VECTOR]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[UMULH]], [[BUILD_VECTOR1]](<4 x s32>)
; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%c1:_(s32) = G_CONSTANT i32 104
%c2:_(s32) = G_CONSTANT i32 72
%1:_(<4 x s32>) = G_BUILD_VECTOR %c1(s32), %c2(s32), %c1(s32), %c2(s32)
%3:_(<4 x s32>) = exact G_UDIV %0, %1
$q0 = COPY %3(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: div_v4s32_splat
body: |
bb.1:
liveins: $q0
; CHECK-LABEL: name: div_v4s32_splat
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1321528399
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<4 x s32>) = G_UMULH [[COPY]], [[BUILD_VECTOR]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[UMULH]], [[BUILD_VECTOR1]](<4 x s32>)
; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%c1:_(s32) = G_CONSTANT i32 104
%1:_(<4 x s32>) = G_BUILD_VECTOR %c1(s32), %c1(s32), %c1(s32), %c1(s32)
%3:_(<4 x s32>) = exact G_UDIV %0, %1
$q0 = COPY %3(<4 x s32>)
RET_ReallyLR implicit $q0
...
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