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Merge branch 'llvm:main' into vector_update
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@JoshuaMBa
JoshuaMBa committed Jul 17, 2024
2 parents e9fe448 + ead486c commit 4e72ed8
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Showing 5 changed files with 161 additions and 16 deletions.
6 changes: 4 additions & 2 deletions clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
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Expand Up @@ -14,6 +14,7 @@
//
//===---------------------------------------------------------------------===//

#include "clang/Basic/TargetID.h"
#include "clang/Basic/Version.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/BinaryFormat/Magic.h"
Expand Down Expand Up @@ -668,7 +669,8 @@ std::unique_ptr<lto::LTO> createLTO(
ModuleHook Hook = [](size_t, const Module &) { return true; }) {
const llvm::Triple Triple(Args.getLastArgValue(OPT_triple_EQ));
// We need to remove AMD's target-id from the processor if present.
StringRef Arch = Args.getLastArgValue(OPT_arch_EQ).split(":").first;
StringRef TargetID = Args.getLastArgValue(OPT_arch_EQ);
StringRef Arch = clang::getProcessorFromTargetID(Triple, TargetID);
lto::Config Conf;
lto::ThinBackend Backend;
// TODO: Handle index-only thin-LTO
Expand Down Expand Up @@ -712,7 +714,7 @@ std::unique_ptr<lto::LTO> createLTO(

if (SaveTemps) {
std::string TempName = (sys::path::filename(ExecutableName) + "." +
Triple.getTriple() + "." + Arch)
Triple.getTriple() + "." + TargetID)
.str();
Conf.PostInternalizeModuleHook = [=](size_t Task, const Module &M) {
std::string File =
Expand Down
2 changes: 1 addition & 1 deletion compiler-rt/lib/scudo/standalone/string_utils.h
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Expand Up @@ -40,7 +40,7 @@ class ScopedString {
void appendString(int Width, int MaxChars, const char *S);
void appendPointer(u64 ptr_value);

Vector<char> String;
Vector<char, 256> String;
};

void Printf(const char *Format, ...) FORMAT(1, 2);
Expand Down
8 changes: 4 additions & 4 deletions compiler-rt/lib/scudo/standalone/tests/vector_test.cpp
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Expand Up @@ -11,7 +11,7 @@
#include "vector.h"

TEST(ScudoVectorTest, Basic) {
scudo::Vector<int> V;
scudo::Vector<int, 64U> V;
EXPECT_EQ(V.size(), 0U);
V.push_back(42);
EXPECT_EQ(V.size(), 1U);
Expand All @@ -23,7 +23,7 @@ TEST(ScudoVectorTest, Basic) {
}

TEST(ScudoVectorTest, Stride) {
scudo::Vector<scudo::uptr> V;
scudo::Vector<scudo::uptr, 32U> V;
for (scudo::uptr I = 0; I < 1000; I++) {
V.push_back(I);
EXPECT_EQ(V.size(), I + 1U);
Expand All @@ -34,7 +34,7 @@ TEST(ScudoVectorTest, Stride) {
}

TEST(ScudoVectorTest, ResizeReduction) {
scudo::Vector<int> V;
scudo::Vector<int, 64U> V;
V.push_back(0);
V.push_back(0);
EXPECT_EQ(V.size(), 2U);
Expand All @@ -48,7 +48,7 @@ TEST(ScudoVectorTest, ResizeReduction) {

// Verify that if the reallocate fails, nothing new is added.
TEST(ScudoVectorTest, ReallocateFails) {
scudo::Vector<char> V;
scudo::Vector<char, 256U> V;
scudo::uptr capacity = V.capacity();

// Get the current address space size.
Expand Down
17 changes: 8 additions & 9 deletions compiler-rt/lib/scudo/standalone/vector.h
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Expand Up @@ -22,7 +22,7 @@ namespace scudo {
// implementation supports only POD types.
//
// NOTE: This class is not meant to be used directly, use Vector<T> instead.
template <typename T, size_t StaticCapacityBytes> class VectorNoCtor {
template <typename T, size_t StaticNumEntries> class VectorNoCtor {
public:
T &operator[](uptr I) {
DCHECK_LT(I, Size);
Expand Down Expand Up @@ -117,21 +117,20 @@ template <typename T, size_t StaticCapacityBytes> class VectorNoCtor {
uptr CapacityBytes = 0;
uptr Size = 0;

T LocalData[StaticCapacityBytes / sizeof(T)] = {};
T LocalData[StaticNumEntries] = {};
MemMapT ExternalBuffer;
};

template <typename T, size_t StaticCapacityBytes = 256U>
class Vector : public VectorNoCtor<T, StaticCapacityBytes> {
template <typename T, size_t StaticNumEntries>
class Vector : public VectorNoCtor<T, StaticNumEntries> {
public:
// Static capacity should be non-zero
static_assert(StaticCapacityBytes > 0U);
constexpr Vector() { VectorNoCtor<T, StaticCapacityBytes>::init(); }
static_assert(StaticNumEntries > 0U, "");
constexpr Vector() { VectorNoCtor<T, StaticNumEntries>::init(); }
explicit Vector(uptr Count) {
VectorNoCtor<T, StaticCapacityBytes>::init(Count);
VectorNoCtor<T, StaticNumEntries>::init(Count);
this->resize(Count);
}
~Vector() { VectorNoCtor<T, StaticCapacityBytes>::destroy(); }
~Vector() { VectorNoCtor<T, StaticNumEntries>::destroy(); }
// Disallow copies and moves.
Vector(const Vector &) = delete;
Vector &operator=(const Vector &) = delete;
Expand Down
144 changes: 144 additions & 0 deletions llvm/test/Transforms/InstCombine/vector-logical-reductions.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,15 @@ define i1 @reduction_logical_or(<4 x i1> %x) {
ret i1 %r
}

define i1 @reduction_logical_or_nxv2i1(<vscale x 2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_or_nxv2i1(
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_and(<4 x i1> %x) {
; CHECK-LABEL: @reduction_logical_and(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
Expand All @@ -21,6 +30,131 @@ define i1 @reduction_logical_and(<4 x i1> %x) {
ret i1 %r
}

define i1 @reduction_logical_and_nxv2i1(<vscale x 2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_and_nxv2i1(
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_mul(<2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_mul(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.mul.v4i1(<2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_mul_nxv2i1(<vscale x 2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_mul_nxv2i1(
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.mul.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.mul.nxv2i1(<vscale x 2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_xor(<2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_xor(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
; CHECK-NEXT: [[TMP2:%.*]] = call range(i2 0, -1) i2 @llvm.ctpop.i2(i2 [[TMP1]])
; CHECK-NEXT: [[R:%.*]] = trunc i2 [[TMP2]] to i1
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.xor.v4i1(<2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_xor_nxv2i1(<vscale x 2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_xor_nxv2i1(
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_smin(<2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_smin(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
; CHECK-NEXT: [[R:%.*]] = icmp ne i2 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.smin.v4i1(<2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_smin_nxv2i1(<vscale x 2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_smin_nxv2i1(
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_smax(<2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_smax(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.smax.v4i1(<2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_smax_nxv2i1(<vscale x 2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_smax_nxv2i1(
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_umin(<2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_umin(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.umin.v4i1(<2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_umin_nxv2i1(<vscale x 2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_umin_nxv2i1(
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_umax(<2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_umax(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
; CHECK-NEXT: [[R:%.*]] = icmp ne i2 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.umax.v4i1(<2 x i1> %x)
ret i1 %r
}

define i1 @reduction_logical_umax_nxv2i1(<vscale x 2 x i1> %x) {
; CHECK-LABEL: @reduction_logical_umax_nxv2i1(
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> %x)
ret i1 %r
}


define i1 @reduction_logical_or_reverse_nxv2i1(<vscale x 2 x i1> %p) {
; CHECK-LABEL: @reduction_logical_or_reverse_nxv2i1(
; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[P:%.*]])
Expand Down Expand Up @@ -93,5 +227,15 @@ declare i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
declare i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
declare i1 @llvm.vector.reduce.mul.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.mul.v2i1(<2 x i1>)
declare i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.smin.v2i1(<2 x i1>)
declare i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.smax.v2i1(<2 x i1>)
declare i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.umin.v2i1(<2 x i1>)
declare i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.umax.v2i1(<2 x i1>)
declare <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1>)
declare <2 x i1> @llvm.vector.reverse.v2i1(<2 x i1>)

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