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@Poseydon42
Poseydon42 committed Jul 16, 2024
1 parent cf0a6b3 commit 49cf46b
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Showing 12 changed files with 2,820 additions and 3,501 deletions.
112 changes: 48 additions & 64 deletions llvm/test/CodeGen/ARM/scmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,14 +4,12 @@
define i8 @scmp_8_8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-LABEL: scmp_8_8:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movwlt r0, #1
; CHECK-NEXT: movwgt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: movwne r2, #1
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mvnlt r2, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: sub r0, r2, r0
; CHECK-NEXT: bx lr
%1 = call i8 @llvm.scmp(i8 %x, i8 %y)
ret i8 %1
Expand All @@ -20,14 +18,12 @@ define i8 @scmp_8_8(i8 signext %x, i8 signext %y) nounwind {
define i8 @scmp_8_16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-LABEL: scmp_8_16:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movwlt r0, #1
; CHECK-NEXT: movwgt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: movwne r2, #1
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mvnlt r2, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: sub r0, r2, r0
; CHECK-NEXT: bx lr
%1 = call i8 @llvm.scmp(i16 %x, i16 %y)
ret i8 %1
Expand All @@ -36,14 +32,12 @@ define i8 @scmp_8_16(i16 signext %x, i16 signext %y) nounwind {
define i8 @scmp_8_32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: scmp_8_32:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movwlt r0, #1
; CHECK-NEXT: movwgt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: movwne r2, #1
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mvnlt r2, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: sub r0, r2, r0
; CHECK-NEXT: bx lr
%1 = call i8 @llvm.scmp(i32 %x, i32 %y)
ret i8 %1
Expand All @@ -54,16 +48,15 @@ define i8 @scmp_8_64(i64 %x, i64 %y) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r11, lr}
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: subs lr, r2, r0
; CHECK-NEXT: subs lr, r0, r2
; CHECK-NEXT: mov r12, #0
; CHECK-NEXT: sbcs lr, r3, r1
; CHECK-NEXT: sbcs lr, r1, r3
; CHECK-NEXT: mov lr, #0
; CHECK-NEXT: movwlt lr, #1
; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs r0, r3, r1
; CHECK-NEXT: movwlt r12, #1
; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwne r12, #1
; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbcs r0, r1, r3
; CHECK-NEXT: mvnlt r12, #0
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: sub r0, r12, lr
; CHECK-NEXT: pop {r11, pc}
%1 = call i8 @llvm.scmp(i64 %x, i64 %y)
ret i8 %1
Expand All @@ -74,24 +67,23 @@ define i8 @scmp_8_128(i128 %x, i128 %y) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: ldr r5, [sp, #24]
; CHECK-NEXT: mov r12, #0
; CHECK-NEXT: ldr r4, [sp, #24]
; CHECK-NEXT: mov r5, #0
; CHECK-NEXT: ldr r6, [sp, #28]
; CHECK-NEXT: subs r7, r5, r0
; CHECK-NEXT: ldr lr, [sp, #32]
; CHECK-NEXT: sbcs r7, r6, r1
; CHECK-NEXT: ldr r4, [sp, #36]
; CHECK-NEXT: sbcs r7, lr, r2
; CHECK-NEXT: sbcs r7, r4, r3
; CHECK-NEXT: movwlt r12, #1
; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwne r12, #1
; CHECK-NEXT: subs r0, r0, r5
; CHECK-NEXT: sbcs r0, r1, r6
; CHECK-NEXT: sbcs r0, r2, lr
; CHECK-NEXT: sbcs r0, r3, r4
; CHECK-NEXT: mvnlt r12, #0
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: subs r7, r0, r4
; CHECK-NEXT: ldr r12, [sp, #32]
; CHECK-NEXT: sbcs r7, r1, r6
; CHECK-NEXT: ldr lr, [sp, #36]
; CHECK-NEXT: sbcs r7, r2, r12
; CHECK-NEXT: sbcs r7, r3, lr
; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: movwlt r7, #1
; CHECK-NEXT: subs r0, r4, r0
; CHECK-NEXT: sbcs r0, r6, r1
; CHECK-NEXT: sbcs r0, r12, r2
; CHECK-NEXT: sbcs r0, lr, r3
; CHECK-NEXT: movwlt r5, #1
; CHECK-NEXT: sub r0, r5, r7
; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%1 = call i8 @llvm.scmp(i128 %x, i128 %y)
ret i8 %1
Expand All @@ -100,14 +92,12 @@ define i8 @scmp_8_128(i128 %x, i128 %y) nounwind {
define i32 @scmp_32_32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: scmp_32_32:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movwlt r0, #1
; CHECK-NEXT: movwgt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: movwne r2, #1
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mvnlt r2, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: sub r0, r2, r0
; CHECK-NEXT: bx lr
%1 = call i32 @llvm.scmp(i32 %x, i32 %y)
ret i32 %1
Expand All @@ -118,16 +108,15 @@ define i32 @scmp_32_64(i64 %x, i64 %y) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r11, lr}
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: subs lr, r2, r0
; CHECK-NEXT: subs lr, r0, r2
; CHECK-NEXT: mov r12, #0
; CHECK-NEXT: sbcs lr, r3, r1
; CHECK-NEXT: sbcs lr, r1, r3
; CHECK-NEXT: mov lr, #0
; CHECK-NEXT: movwlt lr, #1
; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs r0, r3, r1
; CHECK-NEXT: movwlt r12, #1
; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwne r12, #1
; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbcs r0, r1, r3
; CHECK-NEXT: mvnlt r12, #0
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: sub r0, r12, lr
; CHECK-NEXT: pop {r11, pc}
%1 = call i32 @llvm.scmp(i64 %x, i64 %y)
ret i32 %1
Expand All @@ -146,13 +135,8 @@ define i64 @scmp_64_64(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs r0, r3, r1
; CHECK-NEXT: movwlt r12, #1
; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwne r12, #1
; CHECK-NEXT: cmp lr, #0
; CHECK-NEXT: mvnne r12, #0
; CHECK-NEXT: mvnne lr, #0
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: mov r1, lr
; CHECK-NEXT: sub r0, r12, lr
; CHECK-NEXT: asr r1, r0, #31
; CHECK-NEXT: pop {r11, pc}
%1 = call i64 @llvm.scmp(i64 %x, i64 %y)
ret i64 %1
Expand Down
112 changes: 48 additions & 64 deletions llvm/test/CodeGen/ARM/ucmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,14 +4,12 @@
define i8 @ucmp_8_8(i8 zeroext %x, i8 zeroext %y) nounwind {
; CHECK-LABEL: ucmp_8_8:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movwlo r0, #1
; CHECK-NEXT: movwhi r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: movwne r2, #1
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mvnlo r2, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: sub r0, r2, r0
; CHECK-NEXT: bx lr
%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
ret i8 %1
Expand All @@ -20,14 +18,12 @@ define i8 @ucmp_8_8(i8 zeroext %x, i8 zeroext %y) nounwind {
define i8 @ucmp_8_16(i16 zeroext %x, i16 zeroext %y) nounwind {
; CHECK-LABEL: ucmp_8_16:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movwlo r0, #1
; CHECK-NEXT: movwhi r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: movwne r2, #1
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mvnlo r2, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: sub r0, r2, r0
; CHECK-NEXT: bx lr
%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
ret i8 %1
Expand All @@ -36,14 +32,12 @@ define i8 @ucmp_8_16(i16 zeroext %x, i16 zeroext %y) nounwind {
define i8 @ucmp_8_32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: ucmp_8_32:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movwlo r0, #1
; CHECK-NEXT: movwhi r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: movwne r2, #1
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mvnlo r2, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: sub r0, r2, r0
; CHECK-NEXT: bx lr
%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
ret i8 %1
Expand All @@ -54,16 +48,15 @@ define i8 @ucmp_8_64(i64 %x, i64 %y) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r11, lr}
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: subs lr, r2, r0
; CHECK-NEXT: subs lr, r0, r2
; CHECK-NEXT: mov r12, #0
; CHECK-NEXT: sbcs lr, r3, r1
; CHECK-NEXT: sbcs lr, r1, r3
; CHECK-NEXT: mov lr, #0
; CHECK-NEXT: movwlo lr, #1
; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs r0, r3, r1
; CHECK-NEXT: movwlo r12, #1
; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwne r12, #1
; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbcs r0, r1, r3
; CHECK-NEXT: mvnlo r12, #0
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: sub r0, r12, lr
; CHECK-NEXT: pop {r11, pc}
%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
ret i8 %1
Expand All @@ -74,24 +67,23 @@ define i8 @ucmp_8_128(i128 %x, i128 %y) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: ldr r5, [sp, #24]
; CHECK-NEXT: mov r12, #0
; CHECK-NEXT: ldr r4, [sp, #24]
; CHECK-NEXT: mov r5, #0
; CHECK-NEXT: ldr r6, [sp, #28]
; CHECK-NEXT: subs r7, r5, r0
; CHECK-NEXT: ldr lr, [sp, #32]
; CHECK-NEXT: sbcs r7, r6, r1
; CHECK-NEXT: ldr r4, [sp, #36]
; CHECK-NEXT: sbcs r7, lr, r2
; CHECK-NEXT: sbcs r7, r4, r3
; CHECK-NEXT: movwlo r12, #1
; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwne r12, #1
; CHECK-NEXT: subs r0, r0, r5
; CHECK-NEXT: sbcs r0, r1, r6
; CHECK-NEXT: sbcs r0, r2, lr
; CHECK-NEXT: sbcs r0, r3, r4
; CHECK-NEXT: mvnlo r12, #0
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: subs r7, r0, r4
; CHECK-NEXT: ldr r12, [sp, #32]
; CHECK-NEXT: sbcs r7, r1, r6
; CHECK-NEXT: ldr lr, [sp, #36]
; CHECK-NEXT: sbcs r7, r2, r12
; CHECK-NEXT: sbcs r7, r3, lr
; CHECK-NEXT: mov r7, #0
; CHECK-NEXT: movwlo r7, #1
; CHECK-NEXT: subs r0, r4, r0
; CHECK-NEXT: sbcs r0, r6, r1
; CHECK-NEXT: sbcs r0, r12, r2
; CHECK-NEXT: sbcs r0, lr, r3
; CHECK-NEXT: movwlo r5, #1
; CHECK-NEXT: sub r0, r5, r7
; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
ret i8 %1
Expand All @@ -100,14 +92,12 @@ define i8 @ucmp_8_128(i128 %x, i128 %y) nounwind {
define i32 @ucmp_32_32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: ucmp_32_32:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: movwlo r0, #1
; CHECK-NEXT: movwhi r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: movwne r2, #1
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mvnlo r2, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: sub r0, r2, r0
; CHECK-NEXT: bx lr
%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
ret i32 %1
Expand All @@ -118,16 +108,15 @@ define i32 @ucmp_32_64(i64 %x, i64 %y) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r11, lr}
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: subs lr, r2, r0
; CHECK-NEXT: subs lr, r0, r2
; CHECK-NEXT: mov r12, #0
; CHECK-NEXT: sbcs lr, r3, r1
; CHECK-NEXT: sbcs lr, r1, r3
; CHECK-NEXT: mov lr, #0
; CHECK-NEXT: movwlo lr, #1
; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs r0, r3, r1
; CHECK-NEXT: movwlo r12, #1
; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwne r12, #1
; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbcs r0, r1, r3
; CHECK-NEXT: mvnlo r12, #0
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: sub r0, r12, lr
; CHECK-NEXT: pop {r11, pc}
%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
ret i32 %1
Expand All @@ -146,13 +135,8 @@ define i64 @ucmp_64_64(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs r0, r3, r1
; CHECK-NEXT: movwlo r12, #1
; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwne r12, #1
; CHECK-NEXT: cmp lr, #0
; CHECK-NEXT: mvnne r12, #0
; CHECK-NEXT: mvnne lr, #0
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: mov r1, lr
; CHECK-NEXT: sub r0, r12, lr
; CHECK-NEXT: asr r1, r0, #31
; CHECK-NEXT: pop {r11, pc}
%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
ret i64 %1
Expand Down
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