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Assign register banks to virtual registers. Defs and uses of G_ instructions have register banks exclusively, if they had register class, reassign appropriate register bank. Assign register banks using machine uniformity analysis: SGPR - uniform values and some lane masks VGPR - divergent, non S1, values VCC - divergent S1 values(lane masks) RBSelect does not consider available instructions and, in some cases, G_ instructions with some register bank assignment can't be inst-selected. This is solved in RBLegalize. Exceptions when uniformity analysis does not work: S32/S64 lane masks: - need to end up with SGPR register class after instruction selection - In most cases Uniformity analysis declares them as uniform (forced by tablegen) resulting in sgpr S32/S64 reg bank - When Uniformity analysis declares them as divergent (some phis), use intrinsic lane mask analyzer to still assign sgpr register bank temporal divergence copy: - COPY to vgpr with implicit use of $exec inside of the cycle - this copy is declared as uniform by uniformity analysis - make sure that assigned bank is vgpr Note: uniformity analysis does not consider that registers with vgpr def are divergent (you can have uniform value in vgpr). - TODO: implicit use of $exec could be implemented as indicator that instruction is divergent
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