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refs.bib

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+Reference 1:
+@inproceedings{agarwal_tile_2007,
+	title = {The {Tile} {Processor}: {A} 64-{Core} {Multicore} for {Embedded} {Processing}},
+	booktitle = {11th {Annual} {Workshop} on {High} {Performance} {Embedded} {Computing} ({HPEC})},
+	author = {Agarwal, A.},
+	year = {2007}
+}
+
+Reference 2:
+@inproceedings{Ascia04,
+ author = {Ascia, G. and Catania, V. and Palesi, M.},
+ title = {{Multi-objective} {Mapping} for {Mesh-based} {NoC} {Architectures}},
+ booktitle = {Proc 2nd Int Conf on Hardware/Software Codesign and System Synthesis (CODES+ISSS)},
+ year = {2004},
+ pages = {182--187},
+}
+
+Reference 3:
+@inproceedings{Ayari16,
+	author={R. Ayari and I. Hafnaoui and G. Beltrame and G. Nicolescu}, 
+	booktitle={Int Symposium on Rapid System Prototyping (RSP)}, 
+	title={{Schedulability-guided Exploration of Multi-core Systems}}, 
+	year={2016}
+}
+
+Reference 4:
+@inproceedings{de_dinechin_guaranteed_2014,
+	title = {Guaranteed {Services} of the {NoC} of a {Manycore} {Processor}},
+	booktitle = {Proc {Int} {Workshop} on {Network} on {Chip} {Architectures} (NoCArc)},
+	publisher = {ACM},
+	author = {de Dinechin, B. D. and Durand, Y. and van Amstel, D. and Ghiti, A.},
+	year = {2014},
+	pages = {11--16}
+}
+
+Reference 5:
+@article{deb2002fast,
+  title={A fast and elitist multiobjective genetic algorithm: {NSGA-II}},
+  author={Deb, K. and Pratap, A. and Agarwal, S. and Meyarivan, T.},
+  journal={IEEE Transactions on Evolutionary Computation},
+  volume={6},
+  number={2},
+  pages={182--197},
+  year={2002},
+  publisher={IEEE}
+}
+
+Reference 6:
+@article{indrusiak2014end,
+  title={{End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration}},
+  author={L. S. Indrusiak},
+  journal={Journal of Systems Architecture},
+  volume={60},
+  number={7},
+  pages={553--561},
+  year={2014},
+  publisher={Elsevier}
+}
+
+Reference 7:
+@article{indrusiak2016analysis,
+  title={Analysis of buffering effects on hard real-time priority-preemptive wormhole networks},
+  author={Indrusiak, L. S. and Burns, A. and Nikolic, B.},
+  journal={arXiv:1606.02942},
+  year={2016}
+}
+
+Reference 8:
+@article{kashif2015,
+	title = {{SLA}: {A} {Stage}-{Level} {Latency} {Analysis} for {Real}-{Time} {Communication} in a {Pipelined} {Resource} {Model}},
+	volume = {64},
+	number = {4},
+	journal = {IEEE Trans Comput},
+	author = {Kashif, H. and Gholamian, S. and Patel, H.},
+	year = {2015},
+	pages = {1177--1190}
+}
+
+Reference 9:
+@inproceedings{Mesidis11genetic,
+  title={Genetic mapping of hard real-time applications onto {NoC-based} {MPSoCs}—A first approach},
+  author={Mesidis, P. and Indrusiak, L. S.},
+  booktitle={6th Int Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)},
+  year={2011},
+}
+
+Reference 10:
+@inproceedings{Nikolic13,
+	title = {Are {Virtual} {Channels} the {Bottleneck} of {Priority}-aware {Wormhole}-switched {NoC}-based {Many}-cores?},
+	booktitle = {Proc 21st {Int} {Conf} on {Real}-{Time} {Networks} and {Systems} (RTNS)},
+	author = {Nikolic, B. and Ali, H. I. and Petters, S. M. and Pinho, L. M.},
+	year = {2013},
+	pages = {13--22}
+}
+
+Reference 11:
+@article{Palesi11, 
+	author={M. Palesi and G. Ascia and F. Fazzino and V. Catania}, 
+	journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, 
+	title={Data Encoding Schemes in Networks on Chip}, 
+	year={2011}, 
+	volume={30}, 
+	number={5}, 
+	pages={774-786}, 
+}
+
+Reference 12:
+@inproceedings{Sayuti13real,
+  title={{Real-Time Low-Power Task Mapping in Networks-on-Chip}},
+  author={Sayuti, M Norazizi Sham Mohd and Indrusiak, Leandro Soares},
+  booktitle={IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
+  pages={14--19},
+  year={2013}
+}
+
+Reference 13:
+@inproceedings{Shi08,
+	title = {Real-{Time} {Communication} {Analysis} for {On}-{Chip} {Networks} with {Wormhole} {Switching}},
+	doi = {10.1109/NOCS.2008.4492735},
+	booktitle = {{IEEE}/{ACM} {NOCS} {Symposium}},
+	author = {Shi, Z. and Burns, A.},
+	year = {2008},
+	pages = {161--170}
+}
+
+Reference 14:
+@article{shi2010schedulability,
+title = {{Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching}},
+author = "Z. Shi and A. Burns and L. S. Indrusiak",
+journal = "International Journal of Embedded and Real-Time Communication Systems (IJERTCS)",
+volume = "1",
+number = "2",
+year = "2010",
+publisher = "IGI Global Publishing"
+}
+
+Reference 15:
+@inproceedings{singh2013mapping,
+  title={Mapping on multi/many-core systems: survey of current and emerging trends},
+  author={Singh, A. K. and Shafique, M. and Kumar, A. and Henkel, J.},
+  booktitle={Proc 50th IEEE/ACM Design Automation Conference (DAC)},
+  year={2013}
+}
+
+Reference 16:
+@article{tindell1992allocating,
+  title={Allocating Hard Real-Time Tasks: an {NP-Hard} Problem Made Easy},
+  author={Tindell, K. W. and Burns, A. and Wellings, A. J.},
+  journal={Real-Time Systems},
+  volume={4},
+  number={2},
+  pages={145--165},
+  year={1992},
+  publisher={Springer}
+}
+
+
+Reference 17:
+@article{xiong2017,
+	title = {Extending {Real}-{Time} {Analysis} for {Wormhole} {NoCs}},
+	volume = {66},
+	number={9},
+    pages={1532--1546},
+	journal = {IEEE Trans Comput},
+	author = {Xiong, Q. and Wu, F. and Lu, Z. and Xie, C.},
+	year = {2017}
+}