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Update sipeed_tang_nano_9k.py so serial works #564

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Update sipeed_tang_nano_9k.py so serial works #564

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14 changes: 7 additions & 7 deletions litex_boards/targets/sipeed_tang_nano_9k.py
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Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@ def __init__(self, sys_clk_freq=27e6, bios_flash_offset=0x0,

# SoCCore ----------------------------------------------------------------------------------
# Disable Integrated ROM
kwargs["integrated_rom_size"] = 0
# kwargs["integrated_rom_size"] = 0
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Nano 9K", **kwargs)

# SPI Flash --------------------------------------------------------------------------------
Expand All @@ -82,12 +82,12 @@ def __init__(self, sys_clk_freq=27e6, bios_flash_offset=0x0,
self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)

# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion(
origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
size = 64*kB,
linker = True)
)
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
#self.bus.add_region("rom", SoCRegion(
# origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
# size = 64*kB,
# linker = True)
#)
#self.cpu.set_reset_address(self.bus.regions["rom"].origin)

# HyperRAM ---------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
Expand Down