alinx_ax7010: Review/Cleanup.

litex-hub · Mar 17, 2022 · e952a11 · e952a11
1 parent 3aa1042
commit e952a11
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Showing 2 changed files with 9 additions and 14 deletions.
diff --git a/litex_boards/platforms/alinx_ax7010.py b/litex_boards/platforms/alinx_ax7010.py
@@ -7,28 +7,25 @@
 from litex.build.generic_platform import *
 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
 
-#DDR3 SDRAM, QSPI, UART, IIC, 
 # IOs ----------------------------------------------------------------------------------------------
 
 _io = [
     # Clk / Rst
     ("clk100",    0, Pins("U18"), IOStandard("LVCMOS33")),
-    #("sys_clk",    0, Pins("V15"), IOStandard("LVCMOS33")),
-    #("cpu_reset", 0, Pins("U18"), IOStandard("LVCMOS33")),
 
-    # Leds Done
+    # Leds
     ("user_led", 0, Pins("M14"),  IOStandard("LVCMOS33")),
     ("user_led", 1, Pins("M15"),  IOStandard("LVCMOS33")),
     ("user_led", 2, Pins("K16"),  IOStandard("LVCMOS33")),
     ("user_led", 3, Pins("J18"),  IOStandard("LVCMOS33")),
 
-    # Buttons Done
+    # Buttons
     ("user_btn", 0, Pins("N15"), IOStandard("LVCMOS33")),
     ("user_btn", 1, Pins("N16"), IOStandard("LVCMOS33")),
     ("user_btn", 2, Pins("R17"), IOStandard("LVCMOS33")),
     ("user_btn", 3, Pins("T17"), IOStandard("LVCMOS33")),
 
-    # Serial Done
+    # Serial
     ("serial", 0,
         Subsignal("tx", Pins("W19"), IOStandard("LVCMOS33")),
         Subsignal("rx", Pins("W18"), IOStandard("LVCMOS33")),
@@ -65,10 +62,10 @@
 # Connectors ---------------------------------------------------------------------------------------
 
 _connectors = [
-    ("pmodb", "B12 B12 C12"),
+    ("pmodb",    "B12 B12 C12"),
     ("pmodhdmi", "N18 P19 V20 W20 T20 U20 N20 P20 R18 R16 Y18 Y19 V16"),
-    ("pmodj10", "W19 W18 R14 P14 Y17 Y16 W15 V15 Y14 W14 P18 N17 U15 U14 P16 P15 U17 T16 V18 V17 T15 T14 V13 U13 W13 V12 U12 T12 T10 T11 A20 B19 B20 C20"),
-    ("pmodj11", "F17 F16 F20 F19 G20 G19 H18 J18 L20 L19 M20 M19 K18 K17 J19 K19 H20 J20 L17 L16 M18 M17 D20 D19 E19 E18 G18 G17 H17 H16 G15 H15 J14 K14"),
+    ("pmodj10",  "W19 W18 R14 P14 Y17 Y16 W15 V15 Y14 W14 P18 N17 U15 U14 P16 P15 U17 T16 V18 V17 T15 T14 V13 U13 W13 V12 U12 T12 T10 T11 A20 B19 B20 C20"),
+    ("pmodj11",  "F17 F16 F20 F19 G20 G19 H18 J18 L20 L19 M20 M19 K18 K17 J19 K19 H20 J20 L17 L16 M18 M17 D20 D19 E19 E18 G18 G17 H17 H16 G15 H15 J14 K14"),
 ]
 
 # PMODS --------------------------------------------------------------------------------------------
@@ -83,8 +80,6 @@
     ),
 ]
 
-
-
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(XilinxPlatform):

diff --git a/litex_boards/targets/alinx_ax7010.py b/litex_boards/targets/alinx_ax7010.py
@@ -11,7 +11,7 @@
 
 from migen import *
 
-from litex_boards.platforms import zynq_xc7z010 
+from litex_boards.platforms import ax7010
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.interconnect import axi
@@ -30,7 +30,7 @@ def __init__(self, platform, sys_clk_freq):
         self.clock_domains.cd_sys = ClockDomain()
 
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
-        self.comb += pll.reset.eq(self.rst)# | platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
@@ -79,7 +79,7 @@ def main():
 
     if args.load:
         prog = soc.platform.create_programmer()
-        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"), device=1)
+        prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1)
 
 if __name__ == "__main__":
     main()