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efinix_trion_t120_bga576_dev_kit.py: fixed/rewire rx_ctl/tx_ctl (not …
…compatible with DDIO mode), added message at build time
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Original file line number | Diff line number | Diff line change |
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@@ -7,6 +7,8 @@ | |
# Copyright (c) 2021 Florent Kermarrec <[email protected]> | ||
# SPDX-License-Identifier: BSD-2-Clause | ||
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import time | ||
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from migen import * | ||
from migen.genlib.resetsync import AsyncResetSynchronizer | ||
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@@ -94,6 +96,13 @@ def __init__(self, sys_clk_freq=75e6, | |
if with_ethernet or with_etherbone: | ||
# Use board's Ethernet PHYs. | ||
if not eth_rmii_pmod: | ||
msg = "\n" | ||
msg += "rx_ctl/tx_ctl pads location aren't compatible with DDIO mode.\n" | ||
msg += "An hardware modification must be done:\n" | ||
msg += "- rx_ctl: a wire must be soldered between R120 and R174\n" | ||
msg += "- tx_ctl: a wire must be soldered between ETH1_TXEN (Pad 30) and R173\n" | ||
print(msg) | ||
time.sleep(2) | ||
self.ethphy = LiteEthPHYRGMII( | ||
platform = platform, | ||
clock_pads = platform.request("eth_clocks", eth_phy), | ||
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