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[Python][Z80InstrBuilder] Support the rest of instructions.
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@kosarev
kosarev committed Aug 17, 2024
1 parent dcd3b0c commit f4bc1a3
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Showing 4 changed files with 188 additions and 16 deletions.
27 changes: 27 additions & 0 deletions tests/testsuite.py
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Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,37 @@ def __str__(self):
def runTest(self):
TESTS = (
(b'\xcb\x30', 'sll b'),
(b'\xdd\x24', 'inc ixh'),
(b'\xdd\x2c', 'inc ixl'),
(b'\xfd\x24', 'inc iyh'),
(b'\xfd\x2c', 'inc iyl'),
(b'\xdd\xe5', 'push ix'),
(b'\xfd\xe1', 'pop iy'),
(b'\xdd\xe8', 'ret pe'),
(b'\xed\x00', 'xnop 0xed00'),
(b'\xed\x45', 'retn'),
(b'\xed\x55', 'xretn 0xed55'),
(b'\xed\x4d', 'reti'),
(b'\xed\x4c', 'xneg 0xed4c'),
(b'\xed\x4e', 'xim 0xed4e, 0x0'),
(b'\xed\x4f', 'ld r, a'),
(b'\xed\x50', 'in d, (c)'),
(b'\xed\x63\x00\x00', 'xld 0xed63, (0x0), hl'),
(b'\xed\xa3', 'outi'),
(b'\xed\xb3', 'otir'),
(b'\xed\xab', 'outd'),
(b'\xed\xbb', 'otdr'),
(b'\xed\x67', 'rrd'),
(b'\xed\xa0', 'ldi'),
(b'\xed\xa1', 'cpi'),
(b'\xed\xb1', 'cpir'),
(b'\xed\xb9', 'cpdr'),
(b'\xed\xa9', 'cpd'),
(b'\xed\xa2', 'ini'),
(b'\xed\xb2', 'inir'),
(b'\xed\xaa', 'ind'),
(b'\xed\xba', 'indr'),
(b'\xed\xa8', 'ldd'),
)

builder = z80.Z80InstrBuilder()
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21 changes: 13 additions & 8 deletions z80/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -9,15 +9,20 @@

from ._disasm import _Disasm, Z80InstrBuilder
from ._error import Error
from ._instr import (ADD, ADC, AND, CP, OR, SBC, SUB, XOR, BIT, CALL, CCF, CPL,
DAA, DEC, DI, DJNZ, EI, EX, EXX, HALT, IM, INC, IN, JP,
JR, LD, LDDR, LDIR, NEG, NOP,
from ._instr import (ADD, ADC, AND, CP, CPD, CPDR, CPI, CPIR,
OR, SBC, SUB, XOR, BIT, CALL, CCF, CPL,
DAA, DEC, DI, DJNZ, EI, EX, EXX, HALT, IM, XIM,
INC, IN, IND, INDR, INI, INIR, JP, JR, LD, XLD,
LDD, LDDR, LDI, LDIR, NEG, XNEG, NOP, XNOP,
RLC, RL, RR, RRC, SLA, SLL, SRA,
SRL, OUT, OUTI, POP, PUSH, RES, RET,
RLA, RLCA, RLD, RRA, RRCA,
RST, SCF, SET, A, AF, AF2, CF, M, NC, NZ, PO, P, Z, DE,
BC, HL, IReg, IY, IX, SP, B, C, D, E, H, L, UnknownInstr,
JumpInstr, CallInstr, RetInstr, At, IndexReg, Add)
SRL, OUT, OUTD, OTDR, OUTI, OTIR, POP, PUSH, RES,
RET, RETN, XRETN, RETI,
RLA, RLCA, RLD, RRA, RRD, RRCA,
RST, SCF, SET, A, AF, AF2, CF, M, NC, NZ, PE, PO, P, Z,
DE, BC, HL, IReg, R, IY, IX, SP,
B, C, D, E, H, L, IXH, IXL, IYH, IYL,
UnknownInstr, JumpInstr, CallInstr, RetInstr, At,
IndexReg, Add)
from ._machine import I8080Machine, Z80Machine
from ._main import main
from ._source import _SourceFile
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48 changes: 40 additions & 8 deletions z80/_disasm.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,15 +13,20 @@
import os
import tempfile
from ._error import Error
from ._instr import (ADD, ADC, AND, CP, OR, SBC, SUB, XOR, BIT, CALL, CCF, CPL,
DAA, DEC, DI, DJNZ, EI, EX, EXX, HALT, IM, INC, IN, JP,
JR, LD, LDDR, LDIR, NEG, NOP,
from ._instr import (ADD, ADC, AND, CP, CPD, CPDR, CPI, CPIR,
OR, SBC, SUB, XOR, BIT, CALL, CCF, CPL,
DAA, DEC, DI, DJNZ, EI, EX, EXX, HALT, IM, XIM,
INC, IN, IND, INDR, INI, INIR, JP, JR, LD, XLD,
LDD, LDDR, LDI, LDIR, NEG, XNEG, NOP, XNOP,
RLC, RL, RR, RRC, SLA, SLL, SRA,
SRL, OUT, OUTI, POP, PUSH, RES, RET,
RLA, RLCA, RLD, RRA, RRCA,
RST, SCF, SET, A, AF, AF2, CF, M, NC, NZ, PO, P, Z, DE,
BC, HL, IReg, IY, IX, SP, B, C, D, E, H, L, UnknownInstr,
JumpInstr, CallInstr, RetInstr, At, IndexReg, Add)
SRL, OUT, OUTD, OTDR, OUTI, OTIR, POP, PUSH, RES,
RET, RETN, XRETN, RETI,
RLA, RLCA, RLD, RRA, RRD, RRCA,
RST, SCF, SET, A, AF, AF2, CF, M, NC, NZ, PE, PO, P, Z,
DE, BC, HL, IReg, R, IY, IX, SP,
B, C, D, E, H, L, IXH, IXL, IYH, IYL,
UnknownInstr, JumpInstr, CallInstr, RetInstr, At,
IndexReg, Add)
from ._machine import Z80Machine


Expand Down Expand Up @@ -155,15 +160,29 @@ class Z80InstrBuilder(object):
'exx': EXX,
'halt': HALT,
'im': IM,
'xim': XIM,
'inc': INC,
'in': IN,
'Iind': IND,
'Iindr': INDR,
'Iini': INI,
'Iinir': INIR,
'jp': JP,
'jr': JR,
'ld': LD,
'xld': XLD,
'Lldd': LDD,
'Llddr': LDDR,
'Lldi': LDI,
'Lldir': LDIR,
'Mcpd': CPD,
'Mcpdr': CPDR,
'Mcpi': CPI,
'Mcpir': CPIR,
'neg': NEG,
'xneg': XNEG,
'nop': NOP,
'xnop': XNOP,
'Orlc': RLC,
'Orl': RL,
'Orr': RR,
Expand All @@ -177,16 +196,23 @@ class Z80InstrBuilder(object):
'push': PUSH,
'res': RES,
'ret': RET,
'retn': RETN,
'xretn': XRETN,
'reti': RETI,
'rla': RLA,
'rlca': RLCA,
'rld': RLD,
'rra': RRA,
'rrd': RRD,
'rrca': RRCA,
'rst': RST,
'sbc': SBC,
'scf': SCF,
'set': SET,
'Toutd': OUTD,
'Totdr': OTDR,
'Touti': OUTI,
'Totir': OTIR,
}

__OPS = {
Expand All @@ -198,6 +224,7 @@ class Z80InstrBuilder(object):
'Cm': M,
'Cnc': NC,
'Cnz': NZ,
'Cpe': PE,
'Cpo': PO,
'Cp': P,
'Cz': Z,
Expand All @@ -210,6 +237,7 @@ class Z80InstrBuilder(object):
'Giy': IY,
'hl': HL,
'i': IReg,
'r': R,
'ix': IX,
'iy': IY,
'Pbc': BC,
Expand All @@ -225,6 +253,10 @@ class Z80InstrBuilder(object):
'Re': E,
'Rh': H,
'Rl': L,
'Rixh': IXH,
'Rixl': IXL,
'Riyh': IYH,
'Riyl': IYL,
'sp': SP,
}

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108 changes: 108 additions & 0 deletions z80/_instr.py
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,10 @@ class P(metaclass=CondFlag):
pass


class PE(metaclass=CondFlag):
pass


class PO(metaclass=CondFlag):
pass

Expand Down Expand Up @@ -94,6 +98,10 @@ class IReg(metaclass=Reg):
_str = 'i'


class R(metaclass=Reg):
pass


class AF(metaclass=Reg):
pass

Expand All @@ -118,10 +126,26 @@ class IX(metaclass=IndexReg):
pass


class IXH(metaclass=IndexReg):
pass


class IXL(metaclass=IndexReg):
pass


class IY(metaclass=IndexReg):
pass


class IYH(metaclass=IndexReg):
pass


class IYL(metaclass=IndexReg):
pass


class SP(metaclass=Reg):
pass

Expand Down Expand Up @@ -244,6 +268,22 @@ class CP(Instr):
pass


class CPD(Instr):
pass


class CPDR(Instr):
pass


class CPI(Instr):
pass


class CPIR(Instr):
pass


class CPL(Instr):
pass

Expand Down Expand Up @@ -284,10 +324,30 @@ class IM(Instr):
pass


class XIM(Instr):
pass


class IN(Instr):
pass


class IND(Instr):
pass


class INDR(Instr):
pass


class INI(Instr):
pass


class INIR(Instr):
pass


class INC(Instr):
pass

Expand All @@ -304,10 +364,22 @@ class LD(Instr):
pass


class XLD(Instr):
pass


class LDD(Instr):
pass


class LDDR(Instr):
pass


class LDI(Instr):
pass


class LDIR(Instr):
pass

Expand All @@ -316,10 +388,18 @@ class NEG(Instr):
pass


class XNEG(Instr):
pass


class NOP(Instr):
pass


class XNOP(Instr):
pass


class OR(Instr):
pass

Expand All @@ -328,10 +408,22 @@ class OUT(Instr):
pass


class OUTD(Instr):
pass


class OTDR(Instr):
pass


class OUTI(Instr):
pass


class OTIR(Instr):
pass


class POP(Instr):
pass

Expand All @@ -348,6 +440,18 @@ class RET(RetInstr):
pass


class RETN(RetInstr):
pass


class XRETN(RetInstr):
pass


class RETI(RetInstr):
pass


class RL(Instr):
pass

Expand Down Expand Up @@ -376,6 +480,10 @@ class RRA(Instr):
pass


class RRD(Instr):
pass


class RRC(Instr):
pass

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