fix: TCLKA and TCLKB and EVRU/EVRD clocks.

* TCLKA and TCLKB should use UNIV16,17 and CMLs.
* Better handling of the fractional synthesizer configuration - useful
 for EVRD and EVRU as they do not have all the registers functional.

evrMrmApp/src/drvem.cpp

@@ -286,11 +286,6 @@ try{
 
     } else if(formfactor==formFactor_mTCA) {
 
-        // mapping to TCLKA and TCLKB as UNIV16, 17
-        // we move down to UNIV0, 1
-        outputs[std::make_pair(OutputFPUniv,0)]=new MRMOutput(SB()<<n<<":FrontUnivOut0", this, OutputFPUniv, 16);
-        outputs[std::make_pair(OutputFPUniv,1)]=new MRMOutput(SB()<<n<<":FrontUnivOut1", this, OutputFPUniv, 17);
-
         shortcmls.resize(2);
         shortcmls[0]=new MRMCML(n+":CML0", 0,*this,MRMCML::typeCML,form);
         shortcmls[1]=new MRMCML(n+":CML1", 1,*this,MRMCML::typeCML,form);
@@ -685,7 +680,7 @@ EVRMRM::setSourceTS(TSSource src)
     switch(src){
     case TSSourceInternal:
         // div!=0 selects src internal
-        div=(epicsUInt16)(eclk/clk);
+        div=roundToUInt(eclk/clk, 0xffff);
         break;
     case TSSourceEvent:
         BITCLR(NAT,32, base, Control, Control_tsdbus);
@@ -727,7 +722,14 @@ EVRMRM::clockTSSet(double clk)
     TSSource src=SourceTS();
     double eclk=clock();
 
-    if(clk>eclk*1.01 || clk==0.0)
+    /* There is an issue with this and the embedded EVRs of the mTCA EVM vers
+     * 280b0207. The register holding the fractional synthesizer configuration
+     * word is empty, so eclk always resolves to 0, and so does clk. This messes
+     * up with the delay generators width/delay settings. By removing this check
+     * clockTS() can be used for the calculation of the width/delay.
+     * if(clk>eclk*1.01 || clk==0.0)
+     */
+    if(clk==0.0)
         clk=eclk;
 
     SCOPED_LOCK(evrLock);