fix: PR epics-modules#67 - $(IN)DBus-Sel disable moved to the end of …

…the selection.

The idea behind is to avoid shifting of all Bit-s by 1 (so according to
the request).

evrApp/Db/evrin.db

@@ -120,24 +120,25 @@ record(mbbo, "$(IN)DBus-Sel") {
   field( DTYP, "Obj Prop uint16")
   field( OUT , "@OBJ=$(OBJ), PROP=DBus Mask")
   field( PINI, "YES")
-  field( ZRST, "Disabled")
-  field( ONST, "Bit 0")
-  field( TWST, "Bit 1")
-  field( THST, "Bit 2")
-  field( FRST, "Bit 3")
-  field( FVST, "Bit 4")
-  field( SXST, "Bit 5")
-  field( SVST, "Bit 6")
-  field( EIST, "Bit 7")
-  field( ZRVL, "0x0")
-  field( ONVL, "0x1")
-  field( TWVL, "0x2")
-  field( THVL, "0x4")
-  field( FRVL, "0x8")
-  field( FVVL, "0x10")
-  field( SXVL, "0x20")
-  field( SVVL, "0x40")
-  field( EIVL, "0x80")
+  field( VAL,  "8") # Default value: Disable
+  field( ZRST, "Bit 0")
+  field( ONST, "Bit 1")
+  field( TWST, "Bit 2")
+  field( THST, "Bit 3")
+  field( FRST, "Bit 4")
+  field( FVST, "Bit 5")
+  field( SXST, "Bit 6")
+  field( SVST, "Bit 7")
+  field( EIST, "Disabled")
+  field( ZRVL, "0x1")
+  field( ONVL, "0x2")
+  field( TWVL, "0x4")
+  field( THVL, "0x8")
+  field( FRVL, "0x10")
+  field( FVVL, "0x20")
+  field( SXVL, "0x40")
+  field( SVVL, "0x80")
+  field( EIVL, "0x0")
   field( NISV, "INVALID")
   field( TESV, "INVALID")
   field( ELSV, "INVALID")