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This release updates XED according to Intel's latest APX spec (Rev-04), April 2024. It includes: - Remove promoted SHA and KeyLocker EVEX instructions - Encoding update for URDMSR/UWRMSR - Addition of missing CPUID sensitivity for promoted POPCNT EVEX instruction - Update the handling of EVEX.U and reinterpretation to X4 General: - Enable a secured build using a new `--security-level` mfile.py knob (1->Medium, 2->High, 3->Highest). The default level is 1 (will be raised to 2 in a future release) Please expect performance degradation with level 3. - Drop the ICC/ICL build options using mfile.py Add: - AMX: Support the restriction of illegal register combination (Solves #303) - Disassembler: Print sequential registers using "+(N-1)" notation - Add ENC2 support for Intel APX architecture (TBD: REX2 for EGPR support) - Add ENC2 support for KOP instructions Fix: - ISA definition fixes (APX/MOVDIR64B missing operands, Fix CPUID for SYS{ENTER,EXIT}, fix MMX extensions) - RFLAGS: Fix width definition and wrong duplicated operands for several instructions (Solves #320) - Fix CPL definition for ENQCMDS (Solves #311) - Fix CPL definition for LGDT (Solves #312) - Fix CPL definition for VMCALL (Solves #313) - Several bug fixes and improvements for the ENC2 library. For a list of unsupported IFORMS, please check the `enc2_unsupported_ref.json` file. - Fix build with the clang built of llvm-project trunk (Solves #315) Modify: - Improve Python code quality (Solves #314) (Solves #317) We express our gratitude to all members of the XED community for their valuable contributions. Co-authored-by: marjevan <[email protected]>
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{ | ||
"I86": [ | ||
"XCHG_GPRv_OrAX" | ||
], | ||
"LWP": [ | ||
"LLWPCB_GPRyy", | ||
"LWPINS_GPRyy_GPR32d_IMMd", | ||
"LWPINS_GPRyy_MEMd_IMMd", | ||
"LWPVAL_GPRyy_GPR32d_IMMd", | ||
"LWPVAL_GPRyy_MEMd_IMMd", | ||
"SLWPCB_GPRyy" | ||
], | ||
"MPX": [ | ||
"BNDCL_BND_AGEN", | ||
"BNDCL_BND_GPR32", | ||
"BNDCL_BND_GPR64", | ||
"BNDCN_BND_AGEN", | ||
"BNDCN_BND_GPR32", | ||
"BNDCN_BND_GPR64", | ||
"BNDCU_BND_AGEN", | ||
"BNDCU_BND_GPR32", | ||
"BNDCU_BND_GPR64", | ||
"BNDLDX_BND_MEMbnd32", | ||
"BNDLDX_BND_MEMbnd64", | ||
"BNDMK_BND_AGEN", | ||
"BNDMOV_BND_BND", | ||
"BNDMOV_BND_MEMdq", | ||
"BNDMOV_BND_MEMq", | ||
"BNDMOV_MEMdq_BND", | ||
"BNDMOV_MEMq_BND", | ||
"BNDSTX_MEMbnd32_BND", | ||
"BNDSTX_MEMbnd64_BND" | ||
], | ||
"TBM": [ | ||
"BEXTR_XOP_GPR32d_GPR32d_IMMd", | ||
"BEXTR_XOP_GPR32d_MEMd_IMMd", | ||
"BEXTR_XOP_GPRyy_GPRyy_IMMd", | ||
"BEXTR_XOP_GPRyy_MEMy_IMMd", | ||
"BLCFILL_GPR32d_GPR32d", | ||
"BLCFILL_GPR32d_MEMd", | ||
"BLCFILL_GPRyy_GPRyy", | ||
"BLCFILL_GPRyy_MEMy", | ||
"BLCIC_GPR32d_GPR32d", | ||
"BLCIC_GPR32d_MEMd", | ||
"BLCIC_GPRyy_GPRyy", | ||
"BLCIC_GPRyy_MEMy", | ||
"BLCI_GPR32d_GPR32d", | ||
"BLCI_GPR32d_MEMd", | ||
"BLCI_GPRyy_GPRyy", | ||
"BLCI_GPRyy_MEMy", | ||
"BLCMSK_GPR32d_GPR32d", | ||
"BLCMSK_GPR32d_MEMd", | ||
"BLCMSK_GPRyy_GPRyy", | ||
"BLCMSK_GPRyy_MEMy", | ||
"BLCS_GPR32d_GPR32d", | ||
"BLCS_GPR32d_MEMd", | ||
"BLCS_GPRyy_GPRyy", | ||
"BLCS_GPRyy_MEMy", | ||
"BLSFILL_GPR32d_GPR32d", | ||
"BLSFILL_GPR32d_MEMd", | ||
"BLSFILL_GPRyy_GPRyy", | ||
"BLSFILL_GPRyy_MEMy", | ||
"BLSIC_GPR32d_GPR32d", | ||
"BLSIC_GPR32d_MEMd", | ||
"BLSIC_GPRyy_GPRyy", | ||
"BLSIC_GPRyy_MEMy", | ||
"T1MSKC_GPR32d_GPR32d", | ||
"T1MSKC_GPR32d_MEMd", | ||
"T1MSKC_GPRyy_GPRyy", | ||
"T1MSKC_GPRyy_MEMy", | ||
"TZMSK_GPR32d_GPR32d", | ||
"TZMSK_GPR32d_MEMd", | ||
"TZMSK_GPRyy_GPRyy", | ||
"TZMSK_GPRyy_MEMy" | ||
], | ||
"XOP": [ | ||
"VFRCZPD_XMMdq_MEMdq", | ||
"VFRCZPD_XMMdq_XMMdq", | ||
"VFRCZPD_YMMqq_MEMqq", | ||
"VFRCZPD_YMMqq_YMMqq", | ||
"VFRCZPS_XMMdq_MEMdq", | ||
"VFRCZPS_XMMdq_XMMdq", | ||
"VFRCZPS_YMMqq_MEMqq", | ||
"VFRCZPS_YMMqq_YMMqq", | ||
"VFRCZSD_XMMdq_MEMq", | ||
"VFRCZSD_XMMdq_XMMq", | ||
"VFRCZSS_XMMdq_MEMd", | ||
"VFRCZSS_XMMdq_XMMd", | ||
"VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq", | ||
"VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq", | ||
"VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq", | ||
"VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq", | ||
"VPCOMB_XMMdq_XMMdq_MEMdq_IMMb", | ||
"VPCOMB_XMMdq_XMMdq_XMMdq_IMMb", | ||
"VPCOMD_XMMdq_XMMdq_MEMdq_IMMb", | ||
"VPCOMD_XMMdq_XMMdq_XMMdq_IMMb", | ||
"VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb", | ||
"VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb", | ||
"VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb", | ||
"VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb", | ||
"VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb", | ||
"VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb", | ||
"VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb", | ||
"VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb", | ||
"VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb", | ||
"VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb", | ||
"VPCOMW_XMMdq_XMMdq_MEMdq_IMMb", | ||
"VPCOMW_XMMdq_XMMdq_XMMdq_IMMb", | ||
"VPHADDBD_XMMdq_MEMdq", | ||
"VPHADDBD_XMMdq_XMMdq", | ||
"VPHADDBQ_XMMdq_MEMdq", | ||
"VPHADDBQ_XMMdq_XMMdq", | ||
"VPHADDBW_XMMdq_MEMdq", | ||
"VPHADDBW_XMMdq_XMMdq", | ||
"VPHADDDQ_XMMdq_MEMdq", | ||
"VPHADDDQ_XMMdq_XMMdq", | ||
"VPHADDUBD_XMMdq_MEMdq", | ||
"VPHADDUBD_XMMdq_XMMdq", | ||
"VPHADDUBQ_XMMdq_MEMdq", | ||
"VPHADDUBQ_XMMdq_XMMdq", | ||
"VPHADDUBW_XMMdq_MEMdq", | ||
"VPHADDUBW_XMMdq_XMMdq", | ||
"VPHADDUDQ_XMMdq_MEMdq", | ||
"VPHADDUDQ_XMMdq_XMMdq", | ||
"VPHADDUWD_XMMdq_MEMdq", | ||
"VPHADDUWD_XMMdq_XMMdq", | ||
"VPHADDUWQ_XMMdq_MEMdq", | ||
"VPHADDUWQ_XMMdq_XMMdq", | ||
"VPHADDWD_XMMdq_MEMdq", | ||
"VPHADDWD_XMMdq_XMMdq", | ||
"VPHADDWQ_XMMdq_MEMdq", | ||
"VPHADDWQ_XMMdq_XMMdq", | ||
"VPHSUBBW_XMMdq_MEMdq", | ||
"VPHSUBBW_XMMdq_XMMdq", | ||
"VPHSUBDQ_XMMdq_MEMdq", | ||
"VPHSUBDQ_XMMdq_XMMdq", | ||
"VPHSUBWD_XMMdq_MEMdq", | ||
"VPHSUBWD_XMMdq_XMMdq", | ||
"VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPPERM_XMMdq_XMMdq_MEMdq_XMMdq", | ||
"VPPERM_XMMdq_XMMdq_XMMdq_MEMdq", | ||
"VPPERM_XMMdq_XMMdq_XMMdq_XMMdq", | ||
"VPROTB_XMMdq_MEMdq_IMMb", | ||
"VPROTB_XMMdq_MEMdq_XMMdq", | ||
"VPROTB_XMMdq_XMMdq_IMMb", | ||
"VPROTB_XMMdq_XMMdq_MEMdq", | ||
"VPROTB_XMMdq_XMMdq_XMMdq", | ||
"VPROTD_XMMdq_MEMdq_IMMb", | ||
"VPROTD_XMMdq_MEMdq_XMMdq", | ||
"VPROTD_XMMdq_XMMdq_IMMb", | ||
"VPROTD_XMMdq_XMMdq_MEMdq", | ||
"VPROTD_XMMdq_XMMdq_XMMdq", | ||
"VPROTQ_XMMdq_MEMdq_IMMb", | ||
"VPROTQ_XMMdq_MEMdq_XMMdq", | ||
"VPROTQ_XMMdq_XMMdq_IMMb", | ||
"VPROTQ_XMMdq_XMMdq_MEMdq", | ||
"VPROTQ_XMMdq_XMMdq_XMMdq", | ||
"VPROTW_XMMdq_MEMdq_IMMb", | ||
"VPROTW_XMMdq_MEMdq_XMMdq", | ||
"VPROTW_XMMdq_XMMdq_IMMb", | ||
"VPROTW_XMMdq_XMMdq_MEMdq", | ||
"VPROTW_XMMdq_XMMdq_XMMdq", | ||
"VPSHAB_XMMdq_MEMdq_XMMdq", | ||
"VPSHAB_XMMdq_XMMdq_MEMdq", | ||
"VPSHAB_XMMdq_XMMdq_XMMdq", | ||
"VPSHAD_XMMdq_MEMdq_XMMdq", | ||
"VPSHAD_XMMdq_XMMdq_MEMdq", | ||
"VPSHAD_XMMdq_XMMdq_XMMdq", | ||
"VPSHAQ_XMMdq_MEMdq_XMMdq", | ||
"VPSHAQ_XMMdq_XMMdq_MEMdq", | ||
"VPSHAQ_XMMdq_XMMdq_XMMdq", | ||
"VPSHAW_XMMdq_MEMdq_XMMdq", | ||
"VPSHAW_XMMdq_XMMdq_MEMdq", | ||
"VPSHAW_XMMdq_XMMdq_XMMdq", | ||
"VPSHLB_XMMdq_MEMdq_XMMdq", | ||
"VPSHLB_XMMdq_XMMdq_MEMdq", | ||
"VPSHLB_XMMdq_XMMdq_XMMdq", | ||
"VPSHLD_XMMdq_MEMdq_XMMdq", | ||
"VPSHLD_XMMdq_XMMdq_MEMdq", | ||
"VPSHLD_XMMdq_XMMdq_XMMdq", | ||
"VPSHLQ_XMMdq_MEMdq_XMMdq", | ||
"VPSHLQ_XMMdq_XMMdq_MEMdq", | ||
"VPSHLQ_XMMdq_XMMdq_XMMdq", | ||
"VPSHLW_XMMdq_MEMdq_XMMdq", | ||
"VPSHLW_XMMdq_XMMdq_MEMdq", | ||
"VPSHLW_XMMdq_XMMdq_XMMdq" | ||
] | ||
} |
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