External Release v2023.12.19

This release updates XED according to Intel APX (Rev-03) and Intel AVX10 (Rev-02) architecture specifications, December 2023. General: - The XED user guide was updated with explanations for APX, AVX10, and more (https://intelxed.github.io/) - Updated Python version requirement and documentation to 3.8 (closes #306) Added: - Added new APX promoted instructions: RAO-INT and USER-MSR (APX Arch Spec Rev-03) - Added a complete XED encoder support for Intel APX architecture - APX(CCMPcc/CTESTcc): Added operand parser API that extracts the default-flags-values from XED DFV pseudo-register - Updated APX CPUID sensitivity with additional Legacy/VEX CPUID records - FRED: Added compatibility mode SYSCALL Fixed: - Fixed missing REX2 prefix restriction for several legacy instructions - APX/JMPABS: Added missing RIP suppressed operand - ENC2: Fixed the encoding of instruction's operands - Fixed CPUID records for KEYLOCKER and MOVDIR instructions Modified: - Updated AVX10 CPUID sensitivity of 64-bit KMASK instructions (AVX10 Arch Spec Rev-02) - Improved Python code for genutil.py (resolves #307) Co-authored-by: marjevan <[email protected]>
intelxed · Dec 20, 2023 · 2b5c29a · 2b5c29a
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diff --git a/.github/actions/protex-scan/action.yml b/.github/actions/protex-scan/action.yml
@@ -39,8 +39,8 @@ runs:
   steps:
     - name: protex scan
       run: |
-          python3 .github/scripts/protex.py --project-id ${{ inputs.proj_id }} --url ${{ inputs.server }} \
-            --user ${{ inputs.username }} --pass ${{ inputs.password }} --tool-path ${{ inputs.bdstool_path }}
+          python3 .github/scripts/protex.py --project-id '${{ inputs.proj_id }}' --url '${{ inputs.server }}' \
+            --user '${{ inputs.username }}' --pass '${{ inputs.password }}' --tool-path '${{ inputs.bdstool_path }}'
       shell: bash
     - name: add comment   # uploads protex guidance as pull-request comment
       uses: actions/github-script@v6

diff --git a/.github/scripts/protex.py b/.github/scripts/protex.py
@@ -18,6 +18,7 @@
 #  
 #END_LEGAL
 
+import platform
 import sys
 import argparse
 import utils
@@ -53,20 +54,27 @@ def setup():
 
     env = setup()
 
+    os = platform.system()
+    assert os == 'Linux', 'Protex scan is currently only supported on Linux'
+
     # login
-    login_cmd = login_cmd = '{bdstool} --server {url} --user {user} --password {pass} login'.format(**env)
-    utils.run_subprocess(login_cmd)
+    login_cmd = "{bdstool} --server {url} --user {user} --password '{pass}' login".format(**env)
+    rval, rlines = utils.run_subprocess(login_cmd)
+    assert rval == 0, 'login to protex server failed'
 
     # set XED project (basically chooses which project to analyze and create a new workflow for)
     set_project_cmd = '{bdstool} new-project {project_id}'.format(**env)
-    utils.run_subprocess(set_project_cmd)
+    rval, rlines = utils.run_subprocess(set_project_cmd)
+    assert rval == 0, 'xed protex project checkout failed'
 
     # analyze XED
     analyze_cmd = f'{env["bdstool"]} analyze --verbose --path .'
-    utils.run_subprocess(analyze_cmd)
+    rval, rlines = utils.run_subprocess(analyze_cmd)
+    assert rval == 0, 'protex analysis failed'
 
     # logout
     logout_cmd = f'{env["bdstool"]} logout'
-    utils.run_subprocess(logout_cmd)
+    rval, rlines = utils.run_subprocess(logout_cmd)
+    assert rval == 0, 'logout from protex server failed'
 
     sys.exit(0)
diff --git a/.github/workflows/sanity_external.yml b/.github/workflows/sanity_external.yml
@@ -25,7 +25,7 @@ env:
   BASH_ENV: "/tmp_proj/sde_admin/.bashrc_xed"
 
   # XED minimal python version requirement
-  MIN_PY_VER: "3.7.16"
+  MIN_PY_VER: "3.8.17"
 ###########################################################
 
 

diff --git a/Security.md b/Security.md
@@ -0,0 +1,6 @@
+# Security Policy
+Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation. 
+
+## Reporting a Vulnerability
+Please report any security vulnerabilities in this project [utilizing the guidelines here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html).
+
diff --git a/VERSION b/VERSION
@@ -1 +1 @@
-v2023.10.11
+v2023.12.19
diff --git a/datafiles/amd/xed-amd-base.txt b/datafiles/amd/xed-amd-base.txt
@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2020 Intel Corporation
+#Copyright (c) 2023 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -18,10 +18,10 @@
 # file: xed-amd-base.txt
 
 INSTRUCTIONS()::
-# SYSCALL and SYSRET are supported in 32b mode only on AMD chips
-
+# SYSRET is supported in 32b mode only on AMD chips
 {
 ICLASS    : SYSCALL_AMD
+UNAME     : AMDSYSCALL32
 DISASM    : syscall
 CPL       : 3
 CATEGORY  : SYSCALL

diff --git a/datafiles/apx-f/README.md b/datafiles/apx-f/README.md
@@ -1,49 +1,15 @@
-# General
-Intel&reg; Advanced Performance Extensions (Intel&reg; APX) expands the Intel&reg; 64 instruction set architecture with
-access to more registers and adds various new features that improve general-purpose performance. The
-extensions are designed to provide efficient performance gains across a variety of workloads without
-significantly increasing silicon area or power consumption of the core.
-The main features of Intel&reg; APX include:
-• 16 additional general-purpose registers (GPRs) R16–R31, also referred to as Extended GPRs (EGPRs)
-in this document;
-• Three-operand instruction formats with a new data destination (NDD) register for many integer
-instructions;
-• Conditional ISA improvements: New conditional load, store and compare instructions, combined
-with an option for the compiler to suppress the status flags writes of common instructions;
-• Optimized register state save/restore operations;
-• A new 64-bit absolute direct jump instruction
-
-This file describes XED's support status and comments for APX
-
-## APX instructions definition by Intel&reg; XED
-#### Legacy
-- Instructions with REX2 prefix are not defined with new iforms or new ISA-SETs
-#### EVEX
-- Existing (non-APX) EVEX instructions with EGPRs are not defined with new iforms or new ISA-SETs
-- Promoted and new instructions are defined with new iforms, using the `_apx` suffix
-- Introduce new `APX_NDD` attribute For NDD (new data destination) instructions with 3 operands
-- Introduce new `APX_NF` attribute For No-Flags instructions
-
 # Intel&reg; XED support status
-## Decoder support
-Intel&reg; XED decoder currently supports:
+## Decoder/Encoder support
+Intel&reg; XED decoder and encoder fully support APX. 
+It includes:
 #### Legacy
 - REX2 prefix and APX extended GPRs (EGPRs)
 #### EVEX 
-- EGPRs decoding for existing instructions
+- APX extended GPRs (EGPRs)
 - All APX-Promoted instructions
 - All APX new instructions
 
-## Encoder support
-Intel&reg; XED encoder supports status:
-#### Legacy
-- :x: No REX2 support
-#### EVEX 
-- :x: No EGPRs support
-- All APX-Promoted instructions
-- All APX new instructions. Note:
-  - {CF,}CMOVcc - Partial support, need to set the NF operand for forms with EVEX.NF=1
-#### ENC2 module
+#### ENC2 module 
 - :x: No ENC2 support for APX. Users should not use this module for APX encoding
 
 
@@ -53,43 +19,10 @@ APX-Promoted instructions require the equivalent Legacy CPUID as well - Those Le
 CPUIDs are not listed by Intel&reg; XED yet (TBD)
 
 
-## Chip-Check support
-Intel&reg; XED chip-check supports the detection of all APX instructions and flavors.
-APX instruction can be:
-- New APX instruction
-- Legacy instruction with REX2 prefix
-- EVEX instruction with EGPR as one of its operands (register or memory)
-- EVEX instruction with ignored EGPR encoding (EVEX.B4 or EVEX.X4 bit is set but ignored). Such encoding causes illegal instruction on non-APX chips. 
-
-
 # Useful APIs
 Numerous examples and vivid explanations regarding APX features can be found in the xed-ex1 example tool.
 
-## Decoder
-1. Users can dynamically disable APX support using the `NO_APX` API:
-    ```c
-    void xed3_operand_set_no_apx(xed_decoded_inst_t* d, 1)
-    ```
-    The API disables support for all APX architecture, including:
-    - EGPRs for Legacy instructions (actually disables REX2 support)
-    - EGPRs for EVEX instructions (for both APX and no-APX instructions). It means no support for the reinterpreted EVEX bits (EGPRs, NDD/NF and more...)
-    - APX new/promoted EVEX instructions
-
-
- ## Encoder
- 1. The `MUST_USE_EVEX` API forces encoding request to the EVEX space. Use it for APX promoted instructions:
-
-    <sub>C Library API</sub>
-    ```c
-    void xed3_operand_set_must_use_evex(xed_decoded_inst_t* d, 1)
-    ```
-
-    <sub>XED command-line tool</sub>
-    ```bash
-    $ xed.exe -set MUST_USE_EVEX 1 ....
-    ```
-
-2. Encode request for promoted No-Flags instruction should be built with the `NF` operand:
+Encode request for promoted No-Flags instruction should be built with the `NF` operand:
 
     <sub>C Library API</sub>
     ```c
@@ -102,16 +35,6 @@ Numerous examples and vivid explanations regarding APX features can be found in
     ```
 
 ## CCMPcc/CTESTcc (Encode/Decode)
-- Introduce new `DFV` 4-bit pseudo-register for "Default Flags Values" (EVEX.[OF, SF, ZF, CF])
-- The register index represents the default flags bits. For example: `DFV10.index == 10 == 0b1010  ->  OF=1, SF=0, ZF=1, CF=0`
-- The DFV pseudo-register should be explicitly defined in an encoder request. For example:
-    ```bash
-    $ xed -64 -e CCMPB r8b r9b dfv14
-    Request: CCMPB MODE:2, REG0:R8B, REG1:R9B, REG2:DFV14, SMODE:2
-    OPERAND ORDER: REG0 REG1 REG2 
-    Encodable! 6254740238C8
-    .byte 0x62,0x54,0x74,0x02,0x38,0xc8
-    ```
-- the official APX assembly syntax is not support yet. 
+The official APX assembly syntax is not supported yet. 
 Current syntax is: `<MNEMONIC> <reg/mem>, <reg/mem/imm>, <dfv>`
 
diff --git a/datafiles/apx-f/apx-evex-enc.txt b/datafiles/apx-f/apx-evex-enc.txt
@@ -29,7 +29,7 @@ SEQUENCE EVEX_ENC_BIND
          EVEX_REXX_ENC_BIND
          EVEX_REXB_ENC_BIND
          EVEX_REXR4_ENC_BIND
-         EVEX_MAP_ENC_BIND
+         EVEX_REXB4_MAP_ENC_BIND
          EVEX_REXW_VVVV_ENC_BIND
          EVEX_U_ENC_BIND
          EVEX_PP_ENC_BIND
@@ -42,7 +42,7 @@ SEQUENCE EVEX_ENC_EMIT
          EVEX_REXX_ENC_EMIT
          EVEX_REXB_ENC_EMIT
          EVEX_REXR4_ENC_EMIT
-         EVEX_MAP_ENC_EMIT
+         EVEX_REXB4_MAP_ENC_EMIT
          EVEX_REXW_VVVV_ENC_EMIT
          EVEX_U_ENC_EMIT
          EVEX_PP_ENC_EMIT
@@ -69,9 +69,12 @@ APX_CC_EVEX_BYTE3_ENC()::
 true ND[d] SCC[ssss] -> 0b000 d ssss
 
 
-EVEX_MAP_ENC()::
-### Extend an existing NT ###
-MAP=4  -> 0b0100
+EVEX_REXB4_MAP_ENC()::
+### Augment EVEX_REXB4_MAP_ENC() in avx512f ###
+MAP=4 mode64 REXB4[e] -> e 0b100
+MAP=4 mode32 REXB4=0  -> 0b0100
+MAP=7 mode64 REXB4[e] -> e 0b111
+MAP=7 mode32 REXB4=0  -> 0b0111
 
 
 ################ Pattern NTs ################ 

diff --git a/datafiles/apx-f/apx-evex-maps.txt b/datafiles/apx-f/apx-evex-maps.txt
@@ -18,4 +18,5 @@
 
 #  name     space   esc  mapopc mapno modrm disp imm opcpos pattern
 evex-map4   evex    N/A   N/A     4    yes   no  var   1    'MAP4'
+evex-map7   evex    N/A   N/A     7    yes   no   4    1    'MAP7'
 
diff --git a/datafiles/apx-f/apx-evgpr-reg-tables.txt b/datafiles/apx-f/apx-evgpr-reg-tables.txt
@@ -18,39 +18,19 @@
 
 
 ###############################################################
-# Support APX EGPRs with the EVEX.vvvvv encoding field
+# Support GPRs encoding using EVEX.vvvvv encoding field
 ###############################################################
-###############################################################
-# Historicity, we use VGPR*_N() NT for both VEX and EVEX instructions as the fifth
-# EVEX.v bit was not in use (max 16 GPRs).
-# Now, with EGPRs support, we should check all five EVEX.vvvvv bits.
-# Create a new operand NT and separates the *GPR*_N NT to VEX and EVEX
-# versions.
-###############################################################
-# GPRs/EGPRs encoded with EVEX.vvvvv. Available only with APX mode64
-
-xed_reg_enum_t VGPRv_N3()::   
-EOSZ=1 | OUTREG=VGPR16_N3() 
-EOSZ=2 | OUTREG=VGPR32_N3()
-EOSZ=3 | OUTREG=VGPR64_N3() 
-
-
-xed_reg_enum_t VGPR8_N3()::
-mode64 | OUTREG=VGPR8_N3_64()
-
-xed_reg_enum_t VGPR16_N3()::
-mode64 | OUTREG=VGPR16_N3_64()
-
-xed_reg_enum_t VGPR32_N3()::
-mode64 | OUTREG=VGPR32_N3_64()
+# EVEX.vvvvv GPRs encoding is only available with APX/mode64 instructions
 
-xed_reg_enum_t VGPR64_N3()::
-mode64 | OUTREG=VGPR64_N3_64()
+xed_reg_enum_t GPRv_N()::
+EOSZ=1 | OUTREG=GPR16_N() 
+EOSZ=2 | OUTREG=GPR32_N()
+EOSZ=3 | OUTREG=GPR64_N() 
 
 
 # It's odd but XED ILD stores the exact bits values of VEXDEST[0-3] and inverts
 # the VEXDEST4 bit.
-xed_reg_enum_t VGPR64_N3_64()::
+xed_reg_enum_t GPR64_N()::
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_RAX
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_RCX
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_RDX
@@ -86,8 +66,7 @@ VEXDEST4=1 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R30 HAS_EGPR=1
 VEXDEST4=1 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R31 HAS_EGPR=1
 
 
-
-xed_reg_enum_t VGPR32_N3_64()::
+xed_reg_enum_t GPR32_N()::
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_EAX
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_ECX
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_EDX
@@ -123,8 +102,7 @@ VEXDEST4=1 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R30D HAS_EGPR=1
 VEXDEST4=1 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R31D HAS_EGPR=1
 
 
-
-xed_reg_enum_t VGPR16_N3_64()::
+xed_reg_enum_t GPR16_N()::
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_AX
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_CX
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_DX
@@ -160,8 +138,7 @@ VEXDEST4=1 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R30W HAS_EGPR=1
 VEXDEST4=1 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R31W HAS_EGPR=1
 
 
-
-xed_reg_enum_t VGPR8_N3_64()::
+xed_reg_enum_t GPR8_N()::
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_AL
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_CL
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_DL
@@ -170,7 +147,6 @@ VEXDEST4=0 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_SPL
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_BPL
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_SIL
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_DIL
-
 VEXDEST4=0 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R8B
 VEXDEST4=0 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R9B
 VEXDEST4=0 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R10B
@@ -188,7 +164,6 @@ VEXDEST4=1 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_R20B HAS_EGPR=1
 VEXDEST4=1 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_R21B HAS_EGPR=1
 VEXDEST4=1 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_R22B HAS_EGPR=1
 VEXDEST4=1 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_R23B HAS_EGPR=1
-
 VEXDEST4=1 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R24B HAS_EGPR=1
 VEXDEST4=1 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R25B HAS_EGPR=1
 VEXDEST4=1 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R26B HAS_EGPR=1
@@ -199,10 +174,9 @@ VEXDEST4=1 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R30B HAS_EGPR=1
 VEXDEST4=1 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R31B HAS_EGPR=1
 
 
-
 ########## APX POP2/PUSH2 ##########
 
-xed_reg_enum_t VGPR64_N3_NORSP()::
+xed_reg_enum_t GPR64_N_NORSP()::
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_RAX
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_RCX
 VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_RDX
@@ -298,3 +272,4 @@ VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_DFV12
 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_DFV13
 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_DFV14
 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_DFV15
+