Improve macos CI

Signed-off-by: Taiju Yamada <[email protected]> Run ci for any push Signed-off-by: Taiju Yamada <[email protected]> add macos-14 Signed-off-by: Taiju Yamada <[email protected]> add libtool Signed-off-by: Taiju Yamada <[email protected]> Fix mach compilation again; fold_constant has to be the same section as crc16_t10dif_copy_pmull Signed-off-by: Taiju Yamada <[email protected]> add libtool dependency for MacOS CI Signed-off-by: Taiju Yamada <[email protected]> Avoid x18 (except igzip_decode_huffman_code_block_aarch64.S) avoid x18 part2 (igzip_decode_huffman_code_block_aarch64.S, maybe x29 is safe, maybe not) Signed-off-by: Taiju Yamada <[email protected]> revert erasure Signed-off-by: Taiju Yamada <[email protected]> Fixed isal_deflate_icf_finish_lvl1 dispatcher Signed-off-by: Taiju Yamada <[email protected]> retry Signed-off-by: Taiju Yamada <[email protected]> Revert "Run ci for any push" This reverts commit 7d9efff. Signed-off-by: Taiju Yamada <[email protected]>
intel · Mar 4, 2024 · bd7fe6c · bd7fe6c
1 parent f36d1ed
commit bd7fe6c
Show file tree

Hide file tree

Showing 10 changed files with 13 additions and 10 deletions.
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -29,7 +29,8 @@ jobs:
       matrix:
         os:
           - ubuntu-latest
-          - macos-latest
+          - macos-13  # x86_64
+          - macos-14  # arm64
         assembler:
           - nasm
     runs-on: ${{ matrix.os }}

diff --git a/crc/aarch64/crc16_t10dif_copy_pmull.S b/crc/aarch64/crc16_t10dif_copy_pmull.S
@@ -379,13 +379,14 @@ v_br1	.req	v5
 	.size	crc16_t10dif_copy_pmull, .-crc16_t10dif_copy_pmull
 #endif
 
-ASM_DEF_RODATA
 	.align	4
 fold_constant:
 	.word 0x87e70000
 	.word 0x00000000
 	.word 0x371d0000
 	.word 0x00000000
+
+ASM_DEF_RODATA
 .shuffle_mask_lanchor = . + 0
 #ifndef __APPLE__
 	.type	shuffle_mask, %object

diff --git a/crc/aarch64/crc16_t10dif_pmull.S b/crc/aarch64/crc16_t10dif_pmull.S
@@ -364,13 +364,14 @@ v_br1			.req	v5
 	.size	crc16_t10dif_pmull, .-crc16_t10dif_pmull
 #endif
 
-ASM_DEF_RODATA
 	.align	4
 fold_constant:
 	.word 0x87e70000
 	.word 0x00000000
 	.word 0x371d0000
 	.word 0x00000000
+
+ASM_DEF_RODATA
 .shuffle_mask_lanchor = . + 0
 #ifndef __APPLE__
 	.type	shuffle_mask, %object

diff --git a/erasure_code/aarch64/gf_6vect_mad_neon.S b/erasure_code/aarch64/gf_6vect_mad_neon.S
@@ -61,7 +61,7 @@ x_tbl3		.req	x15
 x_tbl4		.req	x16
 x_tbl5		.req	x17
 x_tbl6		.req	x_tbl
-x_const		.req	x18
+x_const		.req	x0
 
 /* vectors */
 v_mask0f	.req	v0

diff --git a/igzip/aarch64/igzip_decode_huffman_code_block_aarch64.S b/igzip/aarch64/igzip_decode_huffman_code_block_aarch64.S
@@ -273,7 +273,7 @@ declare Macros
 	declare_generic_reg	arg2,		2, x
 
 	declare_generic_reg	state,		11,x
-	declare_generic_reg	start_out,	18,x
+	declare_generic_reg	start_out,	29,x
 
 	declare_generic_reg	read_in,	3,x
 	declare_generic_reg	read_in_length,	4,w

diff --git a/igzip/aarch64/igzip_deflate_body_aarch64.S b/igzip/aarch64/igzip_deflate_body_aarch64.S
@@ -95,7 +95,7 @@ skip_has_hist:
 	declare_generic_reg	m_out_start,	15,x
 	declare_generic_reg	m_out_end,	16,x
 	declare_generic_reg	m_bits,		17,x
-	declare_generic_reg	m_bit_count,	18,w
+	declare_generic_reg	m_bit_count,	2,w
 
 	declare_generic_reg	start_in,	19,x
 	declare_generic_reg	end_in,		20,x

diff --git a/igzip/aarch64/igzip_deflate_finish_aarch64.S b/igzip/aarch64/igzip_deflate_finish_aarch64.S
@@ -97,7 +97,7 @@ skip_has_hist:
 	declare_generic_reg	m_out_start,	15,x
 	declare_generic_reg	m_out_end,	16,x
 	declare_generic_reg	m_bits,		17,x
-	declare_generic_reg	m_bit_count,	18,w
+	declare_generic_reg	m_bit_count,	2,w
 
 	declare_generic_reg	start_in,	19,x
 	declare_generic_reg	end_in,		20,x

diff --git a/igzip/aarch64/igzip_multibinary_aarch64_dispatcher.c b/igzip/aarch64/igzip_multibinary_aarch64_dispatcher.c
@@ -91,7 +91,7 @@ DEFINE_INTERFACE_DISPATCHER(isal_deflate_icf_finish_lvl1)
 		return PROVIDER_INFO(isal_deflate_icf_finish_hash_hist_aarch64);
 #elif defined(__APPLE__)
 	if (sysctlEnabled(SYSCTL_CRC32_KEY))
-		return PROVIDER_INFO(isal_deflate_icf_body_hash_hist_aarch64);
+		return PROVIDER_INFO(isal_deflate_icf_finish_hash_hist_aarch64);
 #endif
 	return PROVIDER_BASIC(isal_deflate_icf_finish_hash_hist);
 }

diff --git a/igzip/aarch64/isal_deflate_icf_body_hash_hist.S b/igzip/aarch64/isal_deflate_icf_body_hash_hist.S
@@ -107,7 +107,7 @@ void isal_deflate_icf_body_hash_hist_base(struct isal_zstream *stream);
 	declare_generic_reg	param2,		2,x
 
 	/* local variable */
-	declare_generic_reg	level_buf,	18,x
+	declare_generic_reg	level_buf,	17,x
 	declare_generic_reg	avail_in,	13,w
 	declare_generic_reg	end_in,		13,x
 	declare_generic_reg	start_in,	19,x

diff --git a/igzip/aarch64/isal_deflate_icf_finish_hash_hist.S b/igzip/aarch64/isal_deflate_icf_finish_hash_hist.S
@@ -117,7 +117,7 @@ void isal_deflate_icf_finish_hash_hist_aarch64(struct isal_zstream *stream);
 	declare_generic_reg	next_in,		8,x
 	declare_generic_reg	next_out,		10,x
 	declare_generic_reg	next_out_iter,		5,x
-	declare_generic_reg	file_start,		18,x
+	declare_generic_reg	file_start,		17,x
 	declare_generic_reg	last_seen,		14,x
 
 	declare_generic_reg	literal_code,		9,w