Add Apple Silicon Mac support

Author:Taiju Yamada <[email protected]> Re-organized by: Jerry Yu <[email protected]> Change-Id: Ie85a61f8df478327112f452704df112a6167b4ef Signed-off-by: Jerry Yu <[email protected]>
intel · Dec 9, 2020 · 506bfaf · 506bfaf
1 parent 850b10b
commit 506bfaf
Show file tree

Hide file tree

Showing 62 changed files with 971 additions and 183 deletions.
diff --git a/crc/aarch64/crc16_t10dif_copy_pmull.S b/crc/aarch64/crc16_t10dif_copy_pmull.S
@@ -27,11 +27,19 @@
 #  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #########################################################################
 
+#if defined(__APPLE__)
+	#define cdecl(s) _##s
+#else
+	#define cdecl(s) s
+#endif
+
 	.arch armv8-a+crc+crypto
 	.text
 	.align	3
-	.global	crc16_t10dif_copy_pmull
+	.global	cdecl(crc16_t10dif_copy_pmull)
+#ifndef __APPLE__
 	.type	crc16_t10dif_copy_pmull, %function
+#endif
 
 /* uint16_t crc16_t10dif_pmull(uint16_t seed, uint8_t *buf, uint64_t len) */
 
@@ -67,7 +75,7 @@ x_crc16tab		.req	x5
 x_src_saved		.req	x0
 x_dst_saved		.req	x12
 
-crc16_t10dif_copy_pmull:
+cdecl(crc16_t10dif_copy_pmull):
 	cmp	x_len, 1023
 	sub	sp, sp, #16
 	uxth	w_seed, w_seed
@@ -80,11 +88,19 @@ crc16_t10dif_copy_pmull:
 	cmp	x_len, x_tmp
 	bls	.end
 
+#ifndef __APPLE__
 	sxtw	x_counter, w_counter
 	adrp	x_crc16tab, .LANCHOR0
 	sub	x_src, x_src, x_counter
 	sub	x_dst, x_dst, x_counter
 	add	x_crc16tab, x_crc16tab, :lo12:.LANCHOR0
+#else
+	sxtw	x_counter, w_counter
+	adrp	x_crc16tab, .LANCHOR0@PAGE
+	sub	x_src, x_src, x_counter
+	sub	x_dst, x_dst, x_counter
+	add	x_crc16tab, x_crc16tab, .LANCHOR0@PAGEOFF
+#endif
 
 	.align 2
 .crc_table_loop:
@@ -146,8 +162,13 @@ v_tmp3			.req	v16
 	str	q_x2, [x_dst, 32]
 	str	q_x3, [x_dst, 48]
 
+#ifndef __APPLE__
 	adrp	x_tmp, .shuffle_mask_lanchor
 	ldr	q7, [x_tmp, :lo12:.shuffle_mask_lanchor]
+#else
+	adrp	x_tmp, .shuffle_mask_lanchor@PAGE
+	ldr	q7, [x_tmp, .shuffle_mask_lanchor@PAGEOFF]
+#endif
 
 	tbl	v_tmp1.16b, {v_x0.16b}, v7.16b
 	eor	v_x0.16b, v_tmp3.16b, v_tmp1.16b
@@ -371,23 +392,29 @@ v_br1	.req	v5
 	umov	x0, v_x0.d[0]
 	ubfx	x0, x0, 16, 16
 	b	.crc_table_loop_pre
-
+#ifndef __APPLE__
 	.size	crc16_t10dif_copy_pmull, .-crc16_t10dif_copy_pmull
-
-	.section	.rodata
+	.section .rodata
+#else
+  .section __DATA,data
+#endif
 
 	.align	4
 .shuffle_mask_lanchor = . + 0
+#ifndef __APPLE__
 	.type	shuffle_mask, %object
 	.size	shuffle_mask, 16
+#endif
 shuffle_mask:
 	.byte	15, 14, 13, 12, 11, 10, 9, 8
 	.byte	7,   6,  5,  4,  3,  2, 1, 0
 
 	.align	4
 .LANCHOR0 = . + 0
+#ifndef __APPLE__
 	.type	crc16tab, %object
 	.size	crc16tab, 512
+#endif
 crc16tab:
 	.hword  0x0000, 0x8bb7, 0x9cd9, 0x176e, 0xb205, 0x39b2, 0x2edc, 0xa56b
 	.hword  0xEFBD, 0x640a, 0x7364, 0xf8d3, 0x5db8, 0xd60f, 0xc161, 0x4ad6

diff --git a/crc/aarch64/crc16_t10dif_pmull.S b/crc/aarch64/crc16_t10dif_pmull.S
@@ -27,11 +27,19 @@
 #  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #########################################################################
 
+#if defined(__APPLE__)
+	#define cdecl(s) _##s
+#else
+	#define cdecl(s) s
+#endif
+
 	.arch armv8-a+crc+crypto
 	.text
 	.align	3
-	.global	crc16_t10dif_pmull
+	.global	cdecl(crc16_t10dif_pmull)
+#ifndef __APPLE__
 	.type	crc16_t10dif_pmull, %function
+#endif
 
 /* uint16_t crc16_t10dif_pmull(uint16_t seed, uint8_t *buf, uint64_t len) */
 
@@ -65,7 +73,7 @@ x_counter		.req	x3
 x_crc16tab		.req	x4
 x_buf_saved		.req	x0
 
-crc16_t10dif_pmull:
+cdecl(crc16_t10dif_pmull):
 	cmp	x_len, 1023
 	sub	sp, sp, #16
 	uxth	w_seed, w_seed
@@ -78,10 +86,17 @@ crc16_t10dif_pmull:
 	cmp	x_len, x_tmp
 	bls	.end
 
+#ifndef __APPLE__
 	sxtw	x_counter, w_counter
 	adrp	x_crc16tab, .LANCHOR0
 	sub	x_buf, x_buf, x_counter
 	add	x_crc16tab, x_crc16tab, :lo12:.LANCHOR0
+#else
+	sxtw	x_counter, w_counter
+	adrp	x_crc16tab, .LANCHOR0@PAGE
+	sub	x_buf, x_buf, x_counter
+	add	x_crc16tab, x_crc16tab, .LANCHOR0@PAGEOFF
+#endif
 
 	.align 2
 .crc_table_loop:
@@ -136,8 +151,13 @@ v_tmp3			.req	v16
 	ldr	q_x2, [x_buf, 32]
 	ldr	q_x3, [x_buf, 48]
 
+#ifndef __APPLE__
 	adrp	x_tmp, .shuffle_mask_lanchor
 	ldr	q7, [x_tmp, :lo12:.shuffle_mask_lanchor]
+#else
+	adrp	x_tmp, .shuffle_mask_lanchor@PAGE
+	ldr	q7, [x_tmp, .shuffle_mask_lanchor@PAGEOFF]
+#endif
 
 	tbl	v_tmp1.16b, {v_x0.16b}, v7.16b
 	eor	v_x0.16b, v_tmp3.16b, v_tmp1.16b
@@ -353,22 +373,29 @@ v_br1			.req	v5
 	ubfx	x0, x0, 16, 16
 	b	.crc_table_loop_pre
 
+#ifndef __APPLE__
 	.size	crc16_t10dif_pmull, .-crc16_t10dif_pmull
-
 	.section	.rodata
+#else
+	.section __DATA,data
+#endif
 
 	.align	4
 .shuffle_mask_lanchor = . + 0
+#ifndef __APPLE__
 	.type	shuffle_mask, %object
 	.size	shuffle_mask, 16
+#endif
 shuffle_mask:
 	.byte	15, 14, 13, 12, 11, 10, 9, 8
 	.byte	7,   6,  5,  4,  3,  2, 1, 0
 
 	.align	4
 .LANCHOR0 = . + 0
+#ifndef __APPLE__
 	.type	crc16tab, %object
 	.size	crc16tab, 512
+#endif
 crc16tab:
 	.hword  0x0000, 0x8bb7, 0x9cd9, 0x176e, 0xb205, 0x39b2, 0x2edc, 0xa56b
 	.hword  0xEFBD, 0x640a, 0x7364, 0xf8d3, 0x5db8, 0xd60f, 0xc161, 0x4ad6

diff --git a/crc/aarch64/crc32_aarch64_common.h b/crc/aarch64/crc32_aarch64_common.h
@@ -27,8 +27,11 @@
   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **********************************************************************/
 
-
-
+#if defined(__APPLE__)
+	#define cdecl(s) _##s
+#else
+	#define cdecl(s) s
+#endif
 
 .macro	crc32_hw_common		poly_type
 

diff --git a/crc/aarch64/crc32_common_mix_neoverse_n1.S b/crc/aarch64/crc32_common_mix_neoverse_n1.S
@@ -27,6 +27,11 @@
   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **********************************************************************/
 
+#if defined(__APPLE__)
+	#define cdecl(s) _##s
+#else
+	#define cdecl(s) s
+#endif
 
 .macro	declare_var_vector_reg name:req,reg:req
 	\name\()_q	.req	q\reg
@@ -429,4 +434,3 @@ start_final:
 .endif
 	ret
 .endm
-
diff --git a/crc/aarch64/crc32_gzip_refl_3crc_fold.S b/crc/aarch64/crc32_gzip_refl_3crc_fold.S
@@ -88,8 +88,12 @@
 		);
 */
 
-	.global	crc32_gzip_refl_3crc_fold
+	.global	cdecl(crc32_gzip_refl_3crc_fold)
+#ifndef __APPLE__
 	.type	crc32_gzip_refl_3crc_fold, %function
-crc32_gzip_refl_3crc_fold:
+#endif
+cdecl(crc32_gzip_refl_3crc_fold):
 	crc32_3crc_fold	crc32
+#ifndef __APPLE__
 	.size	crc32_gzip_refl_3crc_fold, .-crc32_gzip_refl_3crc_fold
+#endif
diff --git a/crc/aarch64/crc32_gzip_refl_crc_ext.S b/crc/aarch64/crc32_gzip_refl_crc_ext.S
@@ -59,8 +59,12 @@
 	 * uint32_t crc32_gzip_refl_crc_ext(const unsigned char *BUF,
 	 *              uint64_t LEN,uint32_t wCRC);
 	 */
-	.global	crc32_gzip_refl_crc_ext
+	.global	cdecl(crc32_gzip_refl_crc_ext)
+#ifndef __APPLE__
 	.type	crc32_gzip_refl_crc_ext, %function
-crc32_gzip_refl_crc_ext:
+#endif
+cdecl(crc32_gzip_refl_crc_ext):
 	crc32_hw_common	crc32
+#ifndef __APPLE__
 	.size	crc32_gzip_refl_crc_ext, .-crc32_gzip_refl_crc_ext
+#endif
diff --git a/crc/aarch64/crc32_gzip_refl_pmull.h b/crc/aarch64/crc32_gzip_refl_pmull.h
@@ -47,11 +47,17 @@
 .equ	br_high_b2, 0x1
 
 	.text
+#ifndef __APPLE__
 	.section	.rodata
+#else
+  .section	__DATA,data
+#endif
 	.align	4
 	.set	.lanchor_crc_tab,. + 0
+#ifndef __APPLE__
 	.type	crc32_table_gzip_refl, %object
 	.size	crc32_table_gzip_refl, 1024
+#endif
 crc32_table_gzip_refl:
 	.word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3
 	.word 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91

diff --git a/crc/aarch64/crc32_ieee_norm_pmull.h b/crc/aarch64/crc32_ieee_norm_pmull.h
@@ -47,11 +47,17 @@
 .equ	br_high_b2, 0x1
 
 	.text
+#ifndef __APPLE__
 	.section	.rodata
+#else
+	.section	__DATA,data
+#endif
 	.align	4
 	.set	.lanchor_crc_tab,. + 0
+#ifndef __APPLE__
 	.type	crc32_table_ieee_norm, %object
 	.size	crc32_table_ieee_norm, 1024
+#endif
 crc32_table_ieee_norm:
 	.word 0x00000000, 0x04c11db7, 0x09823b6e, 0x0d4326d9, 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005
 	.word 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd

diff --git a/crc/aarch64/crc32_iscsi_3crc_fold.S b/crc/aarch64/crc32_iscsi_3crc_fold.S
@@ -90,8 +90,12 @@
 
 */
 
-	.global	crc32_iscsi_3crc_fold
+	.global	cdecl(crc32_iscsi_3crc_fold)
+#ifndef __APPLE__
 	.type	crc32_iscsi_3crc_fold, %function
-crc32_iscsi_3crc_fold:
+#endif
+cdecl(crc32_iscsi_3crc_fold):
 	crc32_3crc_fold		crc32c
+#ifndef __APPLE__
 	.size	crc32_iscsi_3crc_fold, .-crc32_iscsi_3crc_fold
+#endif
diff --git a/crc/aarch64/crc32_iscsi_crc_ext.S b/crc/aarch64/crc32_iscsi_crc_ext.S
@@ -58,8 +58,12 @@
 	 * uint32_t crc32_iscsi_crc_ext(const unsigned char *BUF,
 	 *                  uint64_t LEN,uint32_t wCRC);
 	 */
-	.global	crc32_iscsi_crc_ext
+	.global	cdecl(crc32_iscsi_crc_ext)
+#ifndef __APPLE__
 	.type	crc32_iscsi_crc_ext, %function
-crc32_iscsi_crc_ext:
+#endif
+cdecl(crc32_iscsi_crc_ext):
 	crc32_hw_common	crc32c
+#ifndef __APPLE__
 	.size	crc32_iscsi_crc_ext, .-crc32_iscsi_crc_ext
+#endif
diff --git a/crc/aarch64/crc32_iscsi_refl_pmull.S b/crc/aarch64/crc32_iscsi_refl_pmull.S
@@ -35,9 +35,11 @@ crc32_refl_func crc32_iscsi_refl_pmull_internal
 	.arch armv8-a+crc+crypto
 	.text
 	.align 3
-	.global	crc32_iscsi_refl_pmull
+	.global	cdecl(crc32_iscsi_refl_pmull)
+#ifndef __APPLE__
 	.type	crc32_iscsi_refl_pmull, %function
-crc32_iscsi_refl_pmull:
+#endif
+cdecl(crc32_iscsi_refl_pmull):
 	stp	x29, x30, [sp, -32]!
 	mov	x29, sp
 
@@ -47,7 +49,7 @@ crc32_iscsi_refl_pmull:
 	mov	w0, w7
 	mvn	w0, w0
 
-	bl	crc32_iscsi_refl_pmull_internal
+	bl	cdecl(crc32_iscsi_refl_pmull_internal)
 	mvn	w0, w0
 	ldp	x29, x30, [sp], 32
 	ret
diff --git a/crc/aarch64/crc32_iscsi_refl_pmull.h b/crc/aarch64/crc32_iscsi_refl_pmull.h
@@ -47,11 +47,18 @@
 .equ	br_high_b2, 0x0
 
 	.text
+
+#ifndef __APPLE__
 	.section	.rodata
+#else
+  .section	__DATA,data
+#endif
 	.align	4
 	.set	.lanchor_crc_tab,. + 0
+#ifndef __APPLE__
 	.type	crc32_table_iscsi_refl, %object
 	.size	crc32_table_iscsi_refl, 1024
+#endif
 crc32_table_iscsi_refl:
 	.word 0x00000000, 0xF26B8303, 0xE13B70F7, 0x1350F3F4, 0xC79A971F, 0x35F1141C, 0x26A1E7E8, 0xD4CA64EB
 	.word 0x8AD958CF, 0x78B2DBCC, 0x6BE22838, 0x9989AB3B, 0x4D43CFD0, 0xBF284CD3, 0xAC78BF27, 0x5E133C24