[Transform] mlir: named op layout propagation #101
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This was referenced Sep 24, 2024
Merged
| @@ -5,6 +5,7 @@ gc_set_mlir_link_components(MLIR_LINK_COMPONENTS | |||
| gc_add_mlir_library(GcAnalysis | |||
| TargetDescriptionAnalysis.cpp | |||
| MatmulConfigAnalysis.cpp | |||
| GlobalAnalysis.cpp | |||
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Could you please give it a more descriptive name?
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| } else if (isa<tensor::ExpandShapeOp, tensor::CollapseShapeOp, tensor::PadOp>( | ||
| op)) | ||
| return true; | ||
| return false; |
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Suggested change
| } else if (isa<tensor::ExpandShapeOp, tensor::CollapseShapeOp, tensor::PadOp>( | |
| op)) | |
| return true; | |
| return false; | |
| } | |
| return isa<tensor::ExpandShapeOp, tensor::CollapseShapeOp, tensor::PadOp>(op); |
| return false; | ||
| } | ||
|
|
||
| bool hasAllTensorSemantics(linalg::LinalgOp linalgOp) { |
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I think this should be available in some utils already?
| ]; | ||
| } | ||
|
|
||
| def PostProcessPackUnpack : Pass<"post-process-pack-unpack"> { |
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Does it need to be a separate pass if it is a post-processing?
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I'd add tests with the smallest patterns possible just to capture the functionality for all passes and their aspects. They also help to understand what passes do.
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| // copied from mlir | ||
| static SmallVector<int64_t> | ||
| projectToInnerMostNonUnitDimsPos(ArrayRef<int64_t> dimsPos, | ||
| ArrayRef<ReassociationIndices> reassocIndices, | ||
| ArrayRef<int64_t> targetShape) { |
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Could we move it into utils in the upstream?
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| // if forceBlocking is set to true, we will unconditionally convert | ||
| // input/weight/output to blocking layout; otherwise we follow the default | ||
| // heuristic logic |
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| // if forceBlocking is set to true, we will unconditionally convert | |
| // input/weight/output to blocking layout; otherwise we follow the default | |
| // heuristic logic | |
| // if forceBlocking is set to true, we will unconditionally convert | |
| // input/weight/output to blocking layout; otherwise we follow the default | |
| // heuristic logic, which is ?... |
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| if (constantA || curInputLayouts[0].isBlocking() || (M % iim) || (K % iik) || | ||
| (elementType.isBF16() && | ||
| curInputLayouts[0] == TensorLayout({1, 0}, {}, {}))) { | ||
| ALayouts.emplace_back( | ||
| APackInfo.first, APackInfo.second, | ||
| SmallVector<OpFoldResult>{rewriter.getIndexAttr(iim), | ||
| rewriter.getIndexAttr(iik)}); | ||
| } else { | ||
| ALayouts.emplace_back(APackInfo.first, SmallVector<int64_t>{}, | ||
| SmallVector<OpFoldResult>{}); | ||
| } | ||
| if (constantB || curInputLayouts[1].isBlocking() || K % iik || N % iin || | ||
| elementType.isBF16()) { | ||
| BLayouts.emplace_back( | ||
| BPackInfo.first, BPackInfo.second, | ||
| SmallVector<OpFoldResult>{rewriter.getIndexAttr(iik), | ||
| rewriter.getIndexAttr(iin)}); |
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Can there be some abstraction here to avoid platform specificity?
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| } else if (isa<linalg::SoftmaxOp>(linalgOp) || isa<linalg::MapOp>(linalgOp) || | ||
| isa<linalg::YieldOp>(linalgOp) || isa<linalg::IndexOp>(linalgOp)) { |
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Should it fail on generics too?
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| if (failed(packVNNIMMT4D(rewriter, linalgOp))) | ||
| return failure(); | ||
| return success(); |
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Suggested change
| if (failed(packVNNIMMT4D(rewriter, linalgOp))) | |
| return failure(); | |
| return success(); | |
| return packVNNIMMT4D(rewriter, linalgOp); |
lmontigny
approved these changes
Oct 15, 2024
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Add layout propagation related passes.
Tracking: #42