Update README.md

README.md

@@ -47,8 +47,9 @@ These examples use [ModelSim® and Quartus® Prime from Intel FPGA](http:/
     - Click: Finish
     - From Menu, choose System -> Create Global Reset Netwok
     - In the System Contents view, connect the "clk" port of the "clk_0" clock source to the "clk" port of all other modules (by clicking on the bubble at the wire intersections)
-    - In the System Contents view, connect the "data_master" and "instruction_master" ports of the "nios2_gen2_0" to the "s1" port of the "onchip_memory2_0" module
-    - In the System Contents view, connect the "data_master" port of the "nios2_gen2_0" to the "s1" port to each of the remaining modules
+    - In the System Contents view, connect the "data_master" and the "instruction_master" ports of the "nios2_gen2_0" to the "s1" port of the "onchip_memory2_0" module
+    - In the System Contents view, connect the "data_master" port of the "nios2_gen2_0" to the "s1" port of the "pio_0" and the "timer_0" modules
+    - In the System Contents view, connect the "data_master" port of the "nios2_gen2_0" to the "Avalon Memory Mapped Slave" port of the "jtag_uart_0" module
     - In the System Contents view, connect the "irq" port of the "nios2_gen2_0" to the "irq" port of the "timer_0" then to the "irq" port of the "jtag_uart_0"
     - In the System Contents view, double click in the "Export" field at the row "external_connection" under the "pio_0" module and hit the return key
     - In the System Contents view, double click on the "nios2_gen2_0" core, under the "Vectors" tab, choose "onchip_memory2_0.s1" as the "Reset vector memory" and the "Exception vector memory"