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Rework the intrinsic dependencies for SVE instructions #974
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Actually, the load semantics is still a bit off. There should be |
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The new commit fixes the predicate register read and continuous store: Notice that in the continuous case, the base register is read no matter the result of |
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Thank you so much for taking this over @yuxiliu-arm!
This looks very good! I've added a couple of comments just on the documentation/comments of the code.
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The code looks good to me. As it stands we have two options:
- You rework the commits to clean up the history, or
- We squash all commits.
Otherwise this looks ready and I am happy to merge by the end of the week unless there are any objections.
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Thanks @yuxiliu-arm, I will merge this on Friday unless there any objections. |
bind_data_to_output combines two event structures s1 and s2 and extends the iico_data relation to include edges from the (data) output events of s1 to the output of s2. Signed-off-by: Nikos Nikoleris <[email protected]>
Signed-off-by: Nikos Nikoleris <[email protected]>
Signed-off-by: Nikos Nikoleris <[email protected]>
This change adds branching effects where decisions are made and fixes the iico_data and iico_ctrl relations. Signed-off-by: Nikos Nikoleris <[email protected]>
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Merged into master. Thanks @yuxiliu-arm ! |
Supersedes #963.
iico_ctrl
toAnyActiveElement
checks (for scatter load and gather store)iico_ctrl
toActivePredicateElement
checksiico_order
to SVE store1NEG
instructionExample graph change for
herd/tests/instructions/AArch64.sve/Y01.litmus
:LD1D {Z0.D},P0/Z,[X0]
(load, predicated) before:after:
ST1D {Z0.D},P0,[X0]
(store, predicated) before:after:
For
herd/tests/instructions/AArch64.sve/V16.litmus
'sLD1W {Z2.S},P0/Z,[X1,Z1.S,UXTW #2]
(gather load), before:after:
For
herd/tests/instructions/AArch64.sve/V17.litmus
'sST1W {Z1.S},P0,[X1,Z1.S,UXTW #2]
(scatter store), before:after:
Footnotes
Arm ARM B2.5 SVE memory ordering relaxations, R_CJHWV: "When a single SVE vector store instruction generates multiple writes to the same location, the instruction ensures that these writes appear in the coherence order for that location, in order of increasing vector element number. No other ordering restrictions apply to memory effects generated by the same SVE store instruction." ↩