Pipelined RISC V Processor on Verilog

This repo contains our lab project for Computer Architecture CE/CS 321L/330L offered Fall 23. We are building a 5-stage pipelined processor capable of executing the Bubble Sort algorithm in Verilog on Vivado. The project consists of the following tasks:

• Writing the bubble sort code using assembly on Venus online and modifying the single-cycle processor architecture to test bubble sorting.

• Pipelining the processor and checking if different instructions are working correctly.

• Introducing hazard detection mechanisms to make sure sorting works correctly.

The overall project report is also included, which provides an efficiency analysis of the algorithm and our way of implementing Bubble Sort.