drm/tegra: rgb: Parameterize pixel clock and DE polarities

For some Tegra devices, like the Samsung SGH-I927, the pixel clock and data enable (DE) signal polarities have to be programmed differently than in the default case. To accommodate this, add support to set the signal polarities for the RGB interface based on the DRM bus flags. Signed-off-by: Maxim Schwalm <[email protected]>
grate-driver · Aug 8, 2023 · 1148070 · 1148070
1 parent 53dc19e
commit 1148070
Show file tree

Hide file tree

Showing 2 changed files with 27 additions and 3 deletions.
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h
@@ -269,9 +269,15 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
 #define  DC_COM_CRC_CONTROL_ENABLE (1 << 0)
 #define DC_COM_CRC_CHECKSUM			0x301
 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
+
 #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
-#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
-#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
+/* DC_COM_PIN_OUTPUT_POLARITY(1) bits */
+#define  LHS_OUTPUT_POLARITY_LOW (1 << 30)
+#define  LVS_OUTPUT_POLARITY_LOW (1 << 28)
+#define  LSC0_OUTPUT_POLARITY_LOW (1 << 24)
+/* DC_COM_PIN_OUTPUT_POLARITY(3) bits */
+#define  LSPI_OUTPUT_POLARITY_LOW (1 << 8)
+
 #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
 #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
 #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))

diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
@@ -101,6 +101,7 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
 {
 	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 	struct tegra_output *output = encoder_to_output(encoder);
+	struct drm_connector *connector = drm_panel_bridge_connector(output->bridge);
 	struct tegra_rgb *rgb = to_rgb(output);
 	u32 value;
 
@@ -109,7 +110,7 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
 	value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
 	tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
 
-	/* configure H- and V-sync signal polarities */
+	/* configure H- and V-sync and pixel clock signal polarities */
 	value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
 
 	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -124,8 +125,25 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 		value |= LVS_OUTPUT_POLARITY_LOW;
 
+	if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
+		value &= ~LSC0_OUTPUT_POLARITY_LOW;
+
+	if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
+		value |= LSC0_OUTPUT_POLARITY_LOW;
+
 	tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
 
+	/* configure DE signal polarities */
+	value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(3));
+
+	if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_HIGH)
+		value &= ~LSPI_OUTPUT_POLARITY_LOW;
+
+	if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
+		value |= LSPI_OUTPUT_POLARITY_LOW;
+
+	tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(3));
+
 	/* XXX: parameterize? */
 	if (of_machine_is_compatible("samsung,i927")) {
 		/* Set DISP_COLOR_SWAP bit to swap red and blue colors */