use 'f4pga utils'

.github/scripts/install.sh

@@ -52,9 +52,6 @@ case "$FPGA_FAM" in
     ctest -R binary_toolchain_test_xc7* -j${MAX_CORES}
   ;;
   eos-s3)
-    heading "Testing installed toolchain on qlf_k4n8"
-    ctest -j${MAX_CORES} -R "quicklogic_toolchain_test_.*_qlf_k4n8" -VV
-    echo "----------------------------------------"
     heading "Testing installed toolchain on ql_eos_s3"
     ctest -j${MAX_CORES} -R "quicklogic_toolchain_test_.*_ql-eos-s3" -VV
   ;;

.github/workflows/Automerge.yml

@@ -25,6 +25,12 @@ jobs:
       - Linux
       - X64
 
+    strategy:
+      fail-fast: false
+      matrix:
+        fam:
+          - xc7
+          - ql
     env:
       MAX_CORES: 80
       GHA_EXTERNAL_DISK: "tools"
@@ -35,7 +41,7 @@ jobs:
       - name: '📤 Download artifact: arch-defs packages'
         uses: actions/download-artifact@v3
         with:
-          name: packages
+          name: packages_${{ matrix.fam }}
           path: './'
 
       - name: 🕐 Timestamp, Hash and packages.list

.github/workflows/Tests.yml

@@ -84,7 +84,7 @@ jobs:
       - name: '📤 Upload artifact: arch-defs packages'
         uses: actions/upload-artifact@v3
         with:
-          name: packages
+          name: packages_${{ matrix.fam }}
           path: '*.tar.xz'
 
       - name: '📤 Upload artifact: plots'

conda_lock.yml

@@ -104,7 +104,7 @@ dependencies:
     - cycler==0.11.0
     - defusedxml==0.7.1
     - edalize @ https://github.com/lowRISC/edalize/archive/ot.zip
-    - f4pga @ https://github.com/chipsalliance/f4pga/archive/main.zip#subdirectory=f4pga
+    - f4pga @ https://github.com/antmicro/f4pga/archive/umarcor/utils.zip#subdirectory=f4pga
     - fasm==0.0.2.post88
     - fasm-utils @ git+https://github.com/QuickLogic-Corp/quicklogic-fasm-utils@3d6a375ddb6b55aaa5a59d99e44a207d4c18709f
     - fonttools==4.33.3

lattice/ice40/utils/ice40_create_ioplace.py

@@ -5,7 +5,7 @@
 import os
 
 import pcf
-from f4pga.utils.vpr_io_place import IoPlace
+from f4pga.aux.utils.vpr_io_place import IoPlace
 
 import csv
 import argparse

quicklogic/common/cmake/quicklogic_device.cmake

@@ -45,9 +45,17 @@ function(QUICKLOGIC_DEFINE_DEVICE_TYPE)
   set(VPR_DB_FILE "db_vpr.pickle")
   set(ARCH_XML "arch.xml")
 
+  # Set FPGA_FAM env var, skip first 3 characters ('ql-')
+  string(SUBSTRING ${DEVICE} 3 -1 FPGA_FAM)
+
   set(DEVICE_DIR_DATA ${DEVICE})
   if(${DEVICE} STREQUAL "ql-pp3")
-    set(DEVICE_DIR_DATA "ql-eos-s3")	# FIXME: use PP3 timing data when it will be available
+	  set(DEVICE_DIR_DATA "ql-eos-s3")	# FIXME: use PP3 timing data when it will be available
+	  set(FPGA_FAM "eos-s3")
+  endif()
+
+  if(${DEVICE} STREQUAL "ql-pp3e")
+	  set(FPGA_FAM "eos-s3")		# FIXME: add support for pp3e in F4PGA build flow
   endif()
 
   # The techfile and routing timing file
@@ -57,7 +65,8 @@ function(QUICKLOGIC_DEFINE_DEVICE_TYPE)
   # Import data from the techfile
   add_custom_command(
     OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${PHY_DB_FILE}
-    COMMAND python3 -m f4pga.utils.quicklogic.pp3.data_import
+    COMMAND ${CMAKE_COMMAND} -E env FPGA_FAM=${FPGA_FAM}
+    f4pga utils data_import
       --techfile ${TECHFILE}
       --routing-timing ${ROUTING_TIMING}
       --db ${PHY_DB_FILE}
@@ -127,7 +136,8 @@ function(QUICKLOGIC_DEFINE_DEVICE_TYPE)
 
   add_custom_command(
     OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${VPR_DB_FILE}
-    COMMAND python3 -m f4pga.utils.quicklogic.pp3.prepare_vpr_database
+    COMMAND ${CMAKE_COMMAND} -E env FPGA_FAM=${FPGA_FAM}
+      f4pga utils prepare_vpr_database
       --phy-db ${PHY_DB_FILE}
       --vpr-db ${VPR_DB_FILE}
       --sdf-dir ${SDF_TIMING_DIR}
@@ -187,7 +197,8 @@ function(QUICKLOGIC_DEFINE_DEVICE_TYPE)
   get_file_target(VPR_DB_TARGET ${VPR_DB_FILE})
   add_custom_command(
     OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${ARCH_XML}
-    COMMAND python3 -m f4pga.utils.quicklogic.pp3.arch_import
+    COMMAND ${CMAKE_COMMAND} -E env FPGA_FAM=${FPGA_FAM}
+      f4pga utils arch_import
       --vpr-db ${VPR_DB_FILE}
       --arch-out ${ARCH_XML}
       --device ${DEVICE}

quicklogic/common/cmake/quicklogic_jlink.cmake

@@ -57,7 +57,7 @@ function(ADD_JLINK_OUTPUT)
   add_custom_command(
     OUTPUT ${WORK_DIR}/${IOMUX_CONFIG}
     COMMAND ${CMAKE_COMMAND} -E env PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils:$PYTHONPATH
-      python3 -m f4pga.utils.quicklogic.pp3.eos-s3.iomux_config
+      f4pga utils iomux_config
         ${IOMUX_CONFIG_ARGS}
         --map ${PINMAP_LOC}
         --output-format jlink

quicklogic/common/cmake/quicklogic_openocd.cmake

@@ -57,7 +57,7 @@ function(ADD_OPENOCD_OUTPUT)
   add_custom_command(
     OUTPUT ${WORK_DIR}/${IOMUX_CONFIG}
     COMMAND ${CMAKE_COMMAND} -E env PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils:$PYTHONPATH
-      python3 -m f4pga.utils.quicklogic.pp3.eos-s3.iomux_config
+      f4pga utils iomux_config
         ${IOMUX_CONFIG_ARGS}
         --map ${PINMAP_LOC}
         --output-format openocd

quicklogic/common/cmake/quicklogic_qlf_arch.cmake

@@ -30,7 +30,7 @@ function(QUICKLOGIC_DEFINE_QLF_ARCH)
   get_target_property_required(QLF_FASM env QLF_FASM)
 
   if("${FAMILY}" STREQUAL "qlf_k4n8")
-    set(REPACKER_PATH "python3 -m f4pga.utils.quicklogic.repacker.repack")
+    set(REPACKER_PATH "f4pga utils repack")
   else()
     set(REPACKER_PATH )
   endif()
@@ -57,7 +57,7 @@ function(QUICKLOGIC_DEFINE_QLF_ARCH)
     # FIXME: Make common for k4n8 and k6n10
     PLACE_TOOL_CMD "${CMAKE_COMMAND} -E env \
       PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils:$PYTHONPATH:${f4pga-arch-defs_SOURCE_DIR}/quicklogic/common/utils \
-      python3 -m f4pga.utils.quicklogic.qlf_k4n8.create_ioplace \
+      f4pga utils create_ioplace \
           --pinmap_xml \${PINMAP_XML} \
           --blif \${OUT_EBLIF} \
           --pcf \${INPUT_IO_FILE} \
@@ -80,8 +80,10 @@ function(QUICKLOGIC_DEFINE_QLF_ARCH)
 
     NET_PATCH_TOOL
       ${REPACKER_PATH}
+    # FIXME: change FPGA_FAM definition once qlf_k4n8 is supported in f4pba build flow
     NET_PATCH_TOOL_CMD "${CMAKE_COMMAND} -E env \
       PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils \
+      FPGA_FAM=eos-s3 \
       \${QUIET_CMD} \${NET_PATCH_TOOL} \
          --net-in \${IN_NET} \
          --eblif-in \${IN_EBLIF} \

quicklogic/pp3/CMakeLists.txt

@@ -48,22 +48,23 @@ define_arch(
 
   RR_PATCH_CMD "\${CMAKE_COMMAND} -E env \
     PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils:$PYTHONPATH \
-    python3 -m f4pga.utils.quicklogic.pp3.routing_import \
+    FPGA_FAM=eos-s3 \
+    f4pga utils routing_import \
         --vpr-db ${CMAKE_CURRENT_BINARY_DIR}/devices/\${DEVICE_TYPE}/db_vpr.pickle \
         --rr-graph-in \${OUT_RRXML_VIRT} \
         --rr-graph-out \${OUT_RRXML_REAL}"
 
   PLACE_TOOL_CMD "${CMAKE_COMMAND} -E env \
     PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils:$PYTHONPATH \
-    python3 -m f4pga.utils.quicklogic.pp3.create_ioplace \
+    f4pga utils create_ioplace \
         --map \${PINMAP} \
         --blif \${OUT_EBLIF} \
         --pcf \${INPUT_IO_FILE} \
         --net \${OUT_NET}"
 
   PLACE_CONSTR_TOOL_CMD "${CMAKE_COMMAND} -E env \
     PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils \
-    python3 -m f4pga.utils.quicklogic.pp3.create_place_constraints \
+    f4pga utils create_place_constraints \
         --map ${f4pga-arch-defs_BINARY_DIR}/quicklogic/${FAMILY_NAME}/\${BOARD}_clkmap.csv \
         --blif \${OUT_EBLIF} \
         --i /dev/stdin \
@@ -86,7 +87,7 @@ define_arch(
   NO_BIT_TO_BIN
   BIT_TO_V_CMD
     "${CMAKE_COMMAND} -E env PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils:${f4pga-arch-defs_SOURCE_DIR}/quicklogic/${FAMILY_NAME}/utils:$PYTHONPATH \
-    python3 -m f4pga.utils.quicklogic.pp3.fasm2bels \${OUT_BITSTREAM}
+    f4pga utils fasm2bels \${OUT_BITSTREAM}
       --phy-db ${CMAKE_CURRENT_BINARY_DIR}/devices/\${DEVICE_TYPE}/db_phy.pickle
       --input-type bitstream
       --output-verilog \${OUT_BIT_VERILOG}

quicklogic/qlf_k4n8/tests/CMakeLists.txt

@@ -6,5 +6,5 @@ add_custom_target(all_qlf_k4n8_tests_adder)
 add_subdirectory(design_flow)
 add_subdirectory(features)
 add_subdirectory(synth_flow)
-add_dependencies(all_quicklogic_tests all_qlf_k4n8_tests_no_adder)
-add_dependencies(all_quicklogic_tests all_qlf_k4n8_tests_adder)
+#add_dependencies(all_quicklogic_tests all_qlf_k4n8_tests_no_adder)
+#add_dependencies(all_quicklogic_tests all_qlf_k4n8_tests_adder)

testarch/yosys.tcl

@@ -13,7 +13,7 @@ write_json $::env(OUT_JSON)
 write_verilog $::env(OUT_SYNTH_V)
 
 design -reset
-exec $::env(PYTHON3) -m f4pga.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
+exec $::env(PYTHON3) -m f4pga.aux.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
 read_json $::env(SYNTH_JSON)
 yosys -import
 opt_clean

utils/pcf_compare.py

@@ -27,7 +27,7 @@
 """
 import argparse
 
-from f4pga.utils.pcf import parse_simple_pcf
+from f4pga.aux.utils.pcf import parse_simple_pcf
 
 
 def main():

xilinx/common/cmake/arch_define.cmake

@@ -146,14 +146,14 @@ function(ADD_XC_ARCH_DEFINE)
         "
     PLACE_TOOL_CMD "${CMAKE_COMMAND} -E env \
     PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils \
-    \${PYTHON3} -m f4pga.utils.xc7.create_ioplace \
+    \${PYTHON3} -m f4pga.aux.utils.xc7.create_ioplace \
         --map \${PINMAP} \
         --blif \${OUT_EBLIF} \
         \${PCF_INPUT_IO_FILE} \
         --net \${OUT_NET}"
     PLACE_CONSTR_TOOL_CMD "${CMAKE_COMMAND} -E env \
     PYTHONPATH=${f4pga-arch-defs_SOURCE_DIR}/utils \
-    \${PYTHON3} -m f4pga.utils.xc7.create_place_constraints \
+    \${PYTHON3} -m f4pga.aux.utils.xc7.create_place_constraints \
         --net \${OUT_NET} \
         --arch \${DEVICE_MERGED_FILE_LOCATION} \
         --blif \${OUT_EBLIF} \

xilinx/common/utils/prjxray_pcf_to_xdc.py

@@ -5,7 +5,7 @@
 
 """
 import argparse
-from f4pga.utils.pcf import parse_simple_pcf
+from f4pga.aux.utils.pcf import parse_simple_pcf
 
 
 def main():