TEST

.gitmodules

@@ -70,6 +70,6 @@
 [submodule "third_party/ql-pp3e"]
 	path = third_party/ql-pp3e
 	url = https://github.com/QuickLogic-Corp/PolarPro3E
-[submodule "quicklogic/common/utils/quicklogic-timings-importer"]
+[submodule "archs/quicklogic/common/utils/quicklogic-timings-importer"]
 	path = archs/quicklogic/common/utils/quicklogic-timings-importer
 	url = https://github.com/QuickLogic-Corp/quicklogic-timings-importer

CMakeLists.txt

@@ -93,10 +93,10 @@ add_subdirectory(tools/vpr)
 add_subdirectory(library)
 # Disable 7-series support in CI because it consumes too much memory.
 if (NOT LIGHT_BUILD)
-  add_subdirectory(xc)
+  add_subdirectory(archs/xc)
 endif()
-add_subdirectory(ice40)
-add_subdirectory(quicklogic)
+add_subdirectory(archs/ice40)
+add_subdirectory(archs/quicklogic)
 add_subdirectory(testarch)
 add_subdirectory(tests)
 

common/cmake/file_targets.cmake

@@ -140,7 +140,7 @@ function(GET_VERILOG_INCLUDES var file)
   # is called during configure step and generated files don't exist yet.
   execute_process(
     COMMAND
-      ${PYTHON_EXECUTABLE} ${symbiflow-arch-defs_SOURCE_DIR}/utils/deps_verilog.py
+      ${PYTHON_EXECUTABLE} ${symbiflow-arch-defs_SOURCE_DIR}/tools/utils/deps_verilog.py
       --file_per_line ${CMAKE_CURRENT_SOURCE_DIR}/${file}
     WORKING_DIRECTORY ${symbiflow-arch-defs_SOURCE_DIR}
     OUTPUT_VARIABLE INCLUDES
@@ -177,7 +177,7 @@ function(GET_XML_INCLUDES var file)
   # is called during configure step and generated files don't exist yet.
   execute_process(
     COMMAND
-      ${PYTHON_EXECUTABLE} ${symbiflow-arch-defs_SOURCE_DIR}/utils/deps_xml.py
+      ${PYTHON_EXECUTABLE} ${symbiflow-arch-defs_SOURCE_DIR}/tools/utils/deps_xml.py
       --file_per_line ${CMAKE_CURRENT_SOURCE_DIR}/${file}
     WORKING_DIRECTORY ${symbiflow-arch-defs_SOURCE_DIR}
     OUTPUT_VARIABLE INCLUDES

conda_lock.yml

@@ -185,7 +185,7 @@ dependencies:
     - -e third_party/liteeth
     - -e third_party/liteiclink
     - -e third_party/migen
-    - -e quicklogic/common/utils/quicklogic-timings-importer
+    - -e archs/quicklogic/common/utils/quicklogic-timings-importer
     - third_party/pythondata-cpu-vexriscv
     - third_party/pythondata-software-compiler_rt
 prefix: /usr/share/miniconda/envs/f4pga_arch_def_base

requirements.txt

@@ -37,7 +37,7 @@ git+https://github.com/chipsalliance/f4pga-rr-graph.git#egg=rr-graph
 -e third_party/liteeth
 -e third_party/liteiclink
 -e third_party/migen
--e quicklogic/common/utils/quicklogic-timings-importer
+-e archs/quicklogic/common/utils/quicklogic-timings-importer
 third_party/pythondata-cpu-vexriscv
 third_party/pythondata-software-compiler_rt