Basic support for riscv

eurecom-s3 · Feb 17, 2024 · 1f13f37 · 1f13f37
1 parent 04e8855
commit 1f13f37
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Showing 2 changed files with 7 additions and 0 deletions.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
@@ -38,6 +38,9 @@
 #include "kvm_riscv.h"
 #include "tcg/tcg.h"
 
+#define SymExpr void*
+#include "RuntimeCommon.h"
+
 /* RISC-V CPU definitions */
 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
 
@@ -1616,6 +1619,8 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
 static void riscv_cpu_init(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
+    memset(cpu->env_exprs, 0, sizeof(cpu->env_exprs));
+    _sym_register_expression_region(cpu->env_exprs, sizeof(cpu->env_exprs));
 
     cpu_set_cpustate_pointers(cpu);
 

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
@@ -390,6 +390,8 @@ struct ArchCPU {
     /* < public > */
     CPUNegativeOffsetState neg;
     CPURISCVState env;
+    /* space for symbolic expressions corresponding to env */
+    void *env_exprs[512 + 1];   /* TCG_MAX_TEMPS + 1 (for NULL) */
 
     char *dyn_csr_xml;
     char *dyn_vreg_xml;