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Make register categories not translatable (#870)
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* Make register categories and names not translatable

Categories are not user-visible, only used as ids for searching, so
translation is an unnecessary complication that can break things.
And the names of registers were never supposed to be translatable.

Fixes #868

* These strings are not to be translated

The register view relies on these strings to keep the right geometry,
and sometimes even for functionality, so they shouldn't be translated.
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@10110111
10110111 authored Jul 25, 2024
1 parent e2139e6 commit 29489ed
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Showing 2 changed files with 41 additions and 41 deletions.
54 changes: 27 additions & 27 deletions plugins/ODbgRegisterView/arch/x86-generic/x86Groups.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,10 +37,10 @@ namespace {
const BitFieldDescription fpuTagDescription = {
7,
{
tr("valid"),
tr("zero"),
tr("special"),
tr("empty"),
"valid",
"zero",
"special",
"empty",
},
{
tr("Tag as used"),
Expand All @@ -56,10 +56,10 @@ const BitFieldDescription fpuTagDescription = {
const BitFieldDescription roundControlDescription = {
4,
{
tr("NEAR"),
tr("DOWN"),
tr(" UP"),
tr("ZERO"),
"NEAR",
"DOWN",
" UP",
"ZERO",
},
{
tr("Round to nearest"),
Expand All @@ -72,10 +72,10 @@ const BitFieldDescription roundControlDescription = {
const BitFieldDescription precisionControlDescription = {
2,
{
tr("24"),
tr("??"),
tr("53"),
tr("64"),
"24",
"??",
"53",
"64",
},
{
tr("Set 24-bit precision"),
Expand All @@ -88,10 +88,10 @@ const BitFieldDescription precisionControlDescription = {
const BitFieldDescription debugRWDescription = {
5,
{
tr("EXEC"),
tr("WRITE"),
tr(" IO"),
tr(" R/W"),
"EXEC",
"WRITE",
" IO",
" R/W",
},
{
tr("Break on execution"),
Expand All @@ -104,10 +104,10 @@ const BitFieldDescription debugRWDescription = {
const BitFieldDescription debugLenDescription = {
1,
{
tr("1"),
tr("2"),
tr("8"),
tr("4"),
"1",
"2",
"8",
"4",
},
{
tr("Set 1-byte length"),
Expand Down Expand Up @@ -152,7 +152,7 @@ void add_precision_mode(RegisterGroup *group, const QModelIndex &index, int row,

void add_puozdi(RegisterGroup *group, const QModelIndex &excRegIndex, const QModelIndex &maskRegIndex, int startRow, int startColumn) {

static const QString exceptions = tr("PUOZDI");
static const QString exceptions = "PUOZDI";

static const std::unordered_map<char, QString> excNames = {
{'P', tr("Precision")},
Expand Down Expand Up @@ -192,14 +192,14 @@ void add_puozdi(RegisterGroup *group, const QModelIndex &excRegIndex, const QMod
}

RegisterGroup *create_eflags(RegisterViewModelBase::Model *model, QWidget *parent) {
const auto catIndex = find_model_category(model, tr("General Status"));
const auto catIndex = find_model_category(model, "General Status");
if (!catIndex.isValid()) {
return nullptr;
}

auto nameIndex = find_model_register(catIndex, tr("RFLAGS"));
auto nameIndex = find_model_register(catIndex, "RFLAGS");
if (!nameIndex.isValid()) {
nameIndex = find_model_register(catIndex, tr("EFLAGS"));
nameIndex = find_model_register(catIndex, "EFLAGS");
}

if (!nameIndex.isValid()) {
Expand All @@ -209,7 +209,7 @@ RegisterGroup *create_eflags(RegisterViewModelBase::Model *model, QWidget *paren
const auto group = new RegisterGroup(tr("EFL"), parent);
constexpr int NameWidth = 3;
int column = 0;
group->insert(0, column, new FieldWidget(tr("EFL"), group));
group->insert(0, column, new FieldWidget("EFL", group));

constexpr int ValueWidth = 8;
const auto valueIndex = nameIndex.sibling(nameIndex.row(), ModelValueColumn);
Expand All @@ -228,7 +228,7 @@ RegisterGroup *create_eflags(RegisterViewModelBase::Model *model, QWidget *paren
}

RegisterGroup *create_expanded_eflags(RegisterViewModelBase::Model *model, QWidget *parent) {
const auto catIndex = find_model_category(model, tr("General Status"));
const auto catIndex = find_model_category(model, "General Status");
if (!catIndex.isValid()) {
return nullptr;
}
Expand Down Expand Up @@ -318,7 +318,7 @@ RegisterGroup *create_fpu_data(RegisterViewModelBase::Model *model, QWidget *par
constexpr int TagWidth = 7;
const auto fsrIndex = valid_index(find_model_register(catIndex, FsrName));

const QPersistentModelIndex topIndex = valid_index(find_model_register(fsrIndex, tr("TOP"), ModelValueColumn));
const QPersistentModelIndex topIndex = valid_index(find_model_register(fsrIndex, "TOP", ModelValueColumn));

for (int row = 0; row < FpuRegCount; ++row) {
int column = 0;
Expand Down
28 changes: 14 additions & 14 deletions src/arch/x86-generic/RegisterViewModel.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -380,20 +380,20 @@ QVariant RegisterViewModel::data(const QModelIndex &index, int role) const {
*/
RegisterViewModel::RegisterViewModel(int cpuSuppFlags, QObject *parent)
: RegisterViewModelBase::Model(parent),
gprs32(addCategory(tr("General Purpose"))),
gprs64(addCategory(tr("General Purpose"))),
genStatusRegs32(addCategory(tr("General Status"))),
genStatusRegs64(addCategory(tr("General Status"))),
segRegs(addCategory(tr("Segment"))),
dbgRegs32(addCategory(tr("Debug"))),
dbgRegs64(addCategory(tr("Debug"))),
fpuRegs32(addFPUCategory(tr("FPU"))),
fpuRegs64(addFPUCategory(tr("FPU"))),
mmxRegs(addSIMDCategory(tr("MMX"), MMXFormats)),
sseRegs32(addSIMDCategory(tr("SSE"), SSEAVXFormats)),
sseRegs64(addSIMDCategory(tr("SSE"), SSEAVXFormats)),
avxRegs32(addSIMDCategory(tr("AVX"), SSEAVXFormats)),
avxRegs64(addSIMDCategory(tr("AVX"), SSEAVXFormats)) {
gprs32(addCategory("General Purpose")),
gprs64(addCategory("General Purpose")),
genStatusRegs32(addCategory("General Status")),
genStatusRegs64(addCategory("General Status")),
segRegs(addCategory("Segment")),
dbgRegs32(addCategory("Debug")),
dbgRegs64(addCategory("Debug")),
fpuRegs32(addFPUCategory("FPU")),
fpuRegs64(addFPUCategory("FPU")),
mmxRegs(addSIMDCategory("MMX", MMXFormats)),
sseRegs32(addSIMDCategory("SSE", SSEAVXFormats)),
sseRegs64(addSIMDCategory("SSE", SSEAVXFormats)),
avxRegs32(addSIMDCategory("AVX", SSEAVXFormats)),
avxRegs64(addSIMDCategory("AVX", SSEAVXFormats)) {
addGPRs32(gprs32);
addGPRs64(gprs64);

Expand Down

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