Silicon/RK3588: Route PCIe 2 l0 & l1 to the correct Combo PHYs

edk2-porting · Jul 16, 2023 · c206fdf · c206fdf
1 parent f85454f
commit c206fdf
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ComboPhy.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ComboPhy.c
@@ -70,11 +70,11 @@ InitComPhyConfig (
       MmioWrite32 (PhyBaseAddr + (0xd << 2), 0x57);
 
       if (PhyBaseAddr == COMBO_PIPE_PHY0) {
-        MmioWrite32 (PHP_GRF_BASE + PHP_GRF_PCIESEL_CON, BIT0 << 16);
+        MmioWrite32 (PHP_GRF_BASE + PHP_GRF_PCIESEL_CON, BIT1 << 16);
       }
 
       if (PhyBaseAddr == COMBO_PIPE_PHY1) {
-        MmioWrite32 (PHP_GRF_BASE + PHP_GRF_PCIESEL_CON, BIT1 << 16);
+        MmioWrite32 (PHP_GRF_BASE + PHP_GRF_PCIESEL_CON, BIT0 << 16);
       }
       break;