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AArch64: Use dmb limitation enum #20188

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Sep 27, 2024
Merged

AArch64: Use dmb limitation enum #20188

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10 changes: 5 additions & 5 deletions runtime/compiler/aarch64/codegen/ARM64JNILinkage.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ void J9::ARM64::JNILinkage::releaseVMAccess(TR::Node *callNode, TR::Register *vm
// addimmx scratch0, vmThreadReg, #publicFlagsOffset
// movzx scratch1, constReleaseVMAccessOutOfLineMask
//
// dmb ishst
// dmb ish
// loopHead:
// ldxrx scratch2, [scratch0]
// tst scratch2, scratch1
Expand All @@ -93,11 +93,11 @@ void J9::ARM64::JNILinkage::releaseVMAccess(TR::Node *callNode, TR::Register *vm

generateTrg1Src1ImmInstruction(cg(), TR::InstOpCode::addimmx, callNode, scratchReg0, vmThreadReg, fej9->thisThreadGetPublicFlagsOffset());
loadConstant64(cg(), callNode, fej9->constReleaseVMAccessOutOfLineMask(), scratchReg1);
// dmb ishst (Inner Shareable store barrier)
// dmb ish (Inner Shareable full barrier)
// Arm Architecture Reference Manual states:
// "This architecture assumes that all PEs that use the same operating system or hypervisor are in the same Inner Shareable shareability domain"
// thus, inner shareable dmb suffices
generateSynchronizationInstruction(cg(), TR::InstOpCode::dmb, callNode, 0xb);
generateSynchronizationInstruction(cg(), TR::InstOpCode::dmb, callNode, TR::InstOpCode::ish);

TR::LabelSymbol *loopHead = generateLabelSymbol(cg());
generateLabelInstruction(cg(), TR::InstOpCode::label, callNode, loopHead);
Expand Down Expand Up @@ -165,7 +165,7 @@ void J9::ARM64::JNILinkage::acquireVMAccess(TR::Node *callNode, TR::Register *vm
generateTrg1MemSrc1Instruction(cg(), TR::InstOpCode::stxrx, callNode, scratchReg2, TR::MemoryReference::createWithDisplacement(cg(), scratchReg0, 0), scratchReg1);
generateCompareBranchInstruction(cg(), TR::InstOpCode::cbnzx, callNode, scratchReg2, loopHead);
// dmb ishld (Inner Shareable load barrier)
generateSynchronizationInstruction(cg(), TR::InstOpCode::dmb, callNode, 0x9);
generateSynchronizationInstruction(cg(), TR::InstOpCode::dmb, callNode, TR::InstOpCode::ishld);

generateLabelInstruction(cg(), TR::InstOpCode::label, callNode, reacquireVMAccessRestartLabel);
}
Expand Down Expand Up @@ -230,7 +230,7 @@ void J9::ARM64::JNILinkage::acquireVMAccessAtomicFree(TR::Node *callNode, TR::Re
static_assert(static_cast<uint64_t>(J9_PUBLIC_FLAGS_VM_ACCESS) < (1 << 12), "J9_PUBLIC_FLAGS_VM_ACCESS must fit in immediate");
auto strInNativeInstr = generateMemSrc1Instruction(cg(), TR::InstOpCode::strimmx, callNode, TR::MemoryReference::createWithDisplacement(cg(), vmThreadReg, offsetof(J9VMThread, inNative)), zeroReg);
#ifndef J9VM_INTERP_ATOMIC_FREE_JNI_USES_FLUSH
generateSynchronizationInstruction(cg(), TR::InstOpCode::dmb, callNode, 0xb);
generateSynchronizationInstruction(cg(), TR::InstOpCode::dmb, callNode, TR::InstOpCode::ish);
#endif
auto ldrPubliFlagsInstr = generateTrg1MemInstruction(cg(), TR::InstOpCode::ldrimmx, callNode, scratchReg0, TR::MemoryReference::createWithDisplacement(cg(), vmThreadReg, fej9->thisThreadGetPublicFlagsOffset()));
if (debugObj)
Expand Down
39 changes: 15 additions & 24 deletions runtime/compiler/aarch64/codegen/J9TreeEvaluator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -610,8 +610,7 @@ generateSoftwareReadBarrier(TR::Node *node, TR::CodeGenerator *cg, bool isArdbar
if (needSync)
{
// Issue an Acquire barrier after volatile load
// dmb ishld
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0x9);
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ishld);
}

tempMR->decNodeReferenceCounts(cg);
Expand Down Expand Up @@ -1235,16 +1234,14 @@ J9::ARM64::TreeEvaluator::awrtbarEvaluator(TR::Node *node, TR::CodeGenerator *cg
TR::MemoryReference *tempMR = TR::MemoryReference::createWithRootLoadOrStore(cg, node);

// Issue a StoreStore barrier before each volatile store.
// dmb ishst
if (isVolatileMode || isOrderedMode)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0xA);
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ishst);

generateMemSrc1Instruction(cg, TR::InstOpCode::strimmx, node, tempMR, sourceRegister, NULL);

// Issue a StoreLoad barrier after each volatile store.
// dmb ish
if (isVolatileMode)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0xB);
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ish);

wrtbarEvaluator(node, sourceRegister, destinationRegister, firstChild->isNonNull(), cg);

Expand Down Expand Up @@ -1304,16 +1301,14 @@ J9::ARM64::TreeEvaluator::awrtbariEvaluator(TR::Node *node, TR::CodeGenerator *c
TR::MemoryReference *tempMR = TR::MemoryReference::createWithRootLoadOrStore(cg, node);

// Issue a StoreStore barrier before each volatile store.
// dmb ishst
if (isVolatileMode || isOrderedMode)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0xA);
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ishst);

generateMemSrc1Instruction(cg, storeOp, node, tempMR, translatedSrcReg);

// Issue a StoreLoad barrier after each volatile store.
// dmb ish
if (isVolatileMode)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0xB);
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ish);

wrtbarEvaluator(node, sourceRegister, destinationRegister, secondChild->isNonNull(), cg);

Expand Down Expand Up @@ -1557,7 +1552,7 @@ J9::ARM64::TreeEvaluator::monexitEvaluator(TR::Node *node, TR::CodeGenerator *cg
// If there is an AllocationFence directly above this monExit we will not have emitted a
// dmb for the fence.
if (comp->target().isSMP() && cg->getCurrentEvaluationTreeTop()->getPrevTreeTop()->getNode()->getOpCodeValue() == TR::allocationFence)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0xB); // dmb ish (Inner Shareable full barrier)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ish);
return targetRegister;
}

Expand Down Expand Up @@ -1636,7 +1631,7 @@ J9::ARM64::TreeEvaluator::monexitEvaluator(TR::Node *node, TR::CodeGenerator *cg
static const bool useMemoryBarrierForMonitorExit = feGetEnv("TR_aarch64UseMemoryBarrierForMonitorExit") != NULL;
if (useMemoryBarrierForMonitorExit)
{
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0xB); // dmb ish (Inner Shareable full barrier)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ish);
op = fej9->generateCompressedLockWord() ? TR::InstOpCode::strimmw : TR::InstOpCode::strimmx;
}
else
Expand Down Expand Up @@ -2656,36 +2651,32 @@ J9::ARM64::TreeEvaluator::flushEvaluator(TR::Node *node, TR::CodeGenerator *cg)
if (!volatileAccessFound)
{
// StoreStore barrier is required after publishing new object reference to other threads.
// dmb ishst (Inner Shareable store barrier)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0xA);
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ishst);
}
}
}
}
else
{
uint32_t imm;
TR::InstOpCode::AArch64BarrierLimitation lim;
if (op == TR::loadFence)
{
// TR::loadFence is used for both loadLoadFence and acquireFence.
// Loads before the barrier are ordered before loads/stores after the barrier.
// dmb ishld (Inner Shareable load barrier)
imm = 0x9;
lim = TR::InstOpCode::ishld;
}
else if (op == TR::storeFence)
{
// TR::storeFence is used for both storeStoreFence and releaseFence.
// Loads/Stores before the barrier are ordered before stores after the barrier.
// dmb ish (Inner Shareable full barrier)
imm = 0xB;
lim = TR::InstOpCode::ish;
}
else
{
// TR::fullFence is used for fullFence.
// dmb ish (Inner Shareable full barrier)
imm = 0xB;
lim = TR::InstOpCode::ish;
}
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, imm);
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, lim);
}

return NULL;
Expand Down Expand Up @@ -3782,7 +3773,7 @@ J9::ARM64::TreeEvaluator::monentEvaluator(TR::Node *node, TR::CodeGenerator *cg)
generateTrg1MemSrc1Instruction(cg, op, node, tempReg, TR::MemoryReference::createWithDisplacement(cg, addrReg, 0), metaReg);
generateCompareBranchInstruction(cg, TR::InstOpCode::cbnzx, node, tempReg, loopLabel);

generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0xB); // dmb ish (Inner Shareable full barrier)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ish);

srm->reclaimScratchRegister(tempReg);
}
Expand Down Expand Up @@ -4895,7 +4886,7 @@ genCAS(TR::Node *node, TR::CodeGenerator *cg, TR_ARM64ScratchRegisterManager *sr
generateCompareBranchInstruction(cg, TR::InstOpCode::cbnzx, node, resultReg, loopLabel);

if (!casWithoutSync)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, 0xB); // dmb ish (Inner Shareable full barrier)
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ish);

if (createDoneLabel)
{
Expand Down