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llvm: Update baseline to 87cdc8328d6c79da6dcce85eb318296bc5b42e82
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github-actions[bot] committed Oct 8, 2024
1 parent 7ab18dc commit ee3875d
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion llvm/llvm-project
Submodule llvm-project updated 49 files
+2 −0 clang/docs/ReleaseNotes.rst
+7 −3 clang/lib/AST/ByteCode/InterpBuiltin.cpp
+32 −3 clang/lib/AST/DeclCXX.cpp
+22 −14 clang/lib/Headers/avx512fintrin.h
+15 −10 clang/lib/Headers/avxintrin.h
+9 −2 clang/lib/Headers/emmintrin.h
+16 −0 clang/test/CodeGen/X86/avx-builtins.c
+22 −0 clang/test/CodeGen/X86/avx512f-builtins.c
+13 −0 clang/test/CodeGen/X86/sse2-builtins.c
+44 −0 clang/test/Modules/gh110401.cppm
+28 −14 lld/ELF/InputSection.cpp
+32 −0 lld/test/ELF/riscv-pcrel-hilo-error-sections.s
+1 −1 lld/test/ELF/riscv-pcrel-hilo-error.s
+5 −2 llvm/Maintainers.md
+17 −0 llvm/include/llvm/Support/TimeProfiler.h
+2 −1 llvm/lib/Analysis/ConstantFolding.cpp
+3 −2 llvm/lib/IR/ConstantFold.cpp
+85 −31 llvm/lib/Support/TimeProfiler.cpp
+15 −0 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1 −0 llvm/lib/Target/AArch64/AArch64ISelLowering.h
+2 −1 llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+7 −3 llvm/lib/Target/AArch64/AArch64Subtarget.h
+3 −1 llvm/lib/Target/AArch64/SVEInstrFormats.td
+12 −15 llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+201 −0 llvm/test/CodeGen/AArch64/sve2-bf16-converts.ll
+31 −27 llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
+45 −14 llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
+1 −2 llvm/test/Transforms/LoopVectorize/AArch64/interleave-allocsize-not-equal-typesize.ll
+1 −2 llvm/test/Transforms/LoopVectorize/AArch64/interleaved-store-of-first-order-recurrence.ll
+3 −6 llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
+1 −2 llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
+2 −4 llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
+38 −61 llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
+1 −2 llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+2 −4 llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
+4 −8 llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+6 −12 llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
+1 −2 llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
+3 −6 llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-hoist-load-across-store.ll
+2 −4 llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-sink-store-across-load.ll
+1 −2 llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll
+2 −4 llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
+16 −32 llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
+2 −4 llvm/test/Transforms/LoopVectorize/X86/pr56319-vector-exit-cond-optimization-epilogue-vectorization.ll
+2 −4 llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
+1 −2 llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
+1 −2 llvm/test/Transforms/LoopVectorize/X86/vplan-native-inner-loop-only.ll
+2 −4 llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
+24 −0 llvm/unittests/Support/TimeProfilerTest.cpp

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