Skip to content

Commit

Permalink
Fixed VICE test quickreu-test3
Browse files Browse the repository at this point in the history
  • Loading branch information
dirkwhoffmann committed Sep 5, 2024
1 parent 29faf04 commit 4739ea5
Show file tree
Hide file tree
Showing 3 changed files with 31 additions and 11 deletions.
38 changes: 29 additions & 9 deletions Emulator/Media/Cartridges/CustomCartridges/Reu.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -47,14 +47,15 @@ Reu::_dump(Category category, std::ostream& os) const
{
using namespace util;

string mode[4] = { "STASH", "FETCH", "SWAP", "VERIFY" };

Cartridge::_dump(category, os);
os << std::endl;

if (category == Category::State) {

string mode[4] = { "STASH", "FETCH", "SWAP", "VERIFY" };
auto model = isREU1700() ? "1700" : isREU1764() ? "1764" : "1750";

os << std::endl;
os << tab("Model");
os << "REU " << model << std::endl;
os << tab("Capacity");
Expand Down Expand Up @@ -97,6 +98,18 @@ Reu::_dump(Category category, std::ostream& os) const
os << tab("REU address increment");
os << dec(reuStep()) << std::endl;
}

if (category == Category::Dma) {

string symb[4] = { "->", "<-", "<->", "==" };

os << mode[cr & 3] << ": ";
os << "C64: " << hex(c64Base) << (memStep() ? "+ " : " ");
os << symb[cr & 3] << " ";
os << "REU: " << dec(reuBank) << ":" << hex(reuBase) << (reuStep() ? "+ " : " ");
os << "Len: " << dec(tlength);
os << std::endl;
}
}

void
Expand Down Expand Up @@ -223,11 +236,11 @@ Reu::pokeIO2(u16 addr, u8 value)

if (GET_BIT(cr,7) && ff00Enabled()) {

debug(REU_DEBUG, "Preparing for DMA [Mode %d]...\n", cr & 0x3);
// debug(REU_DEBUG, "Preparing for DMA [Mode %d]...\n", cr & 0x3);
}
if (GET_BIT(cr,7) && ff00Disabled()) {

debug(REU_DEBUG, "Initiating DMA [Mode %d]...\n", cr & 0x3);
// debug(REU_DEBUG, "Initiating DMA [Mode %d]...\n", cr & 0x3);
prepareDma();
}
break;
Expand Down Expand Up @@ -311,7 +324,7 @@ Reu::pokeIO2(u16 addr, u8 value)
void
Reu::poke(u16 addr, u8 value)
{
debug(REU_DEBUG, "poke(%x,%x)\n", addr, value);
// debug(REU_DEBUG, "poke(%x,%x)\n", addr, value);
assert((addr & 0xF000) == 0xF000);

if (addr == 0xFF00 && isArmed()) {
Expand Down Expand Up @@ -414,7 +427,7 @@ Reu::incReuAddr()
void
Reu::prepareDma()
{
// if (REU_DEBUG) { dump(Category::Dma, std::cout); }
if (REU_DEBUG) { dump(Category::Dma, std::cout); }

// Update control register bits
cr = (cr & ~CR::EXECUTE) | CR::FF00_DISABLE;
Expand Down Expand Up @@ -502,10 +515,15 @@ Reu::finalizeDma(EventID id)
{
if (autoloadEnabled()) {

debug(REU_DEBUG, "Autoloading...\n");
c64Base = c64BaseLatched;
reuBase = reuBaseLatched;
reuBank = reuBankLatched;
tlength = tlengthLatched;

} else {

debug(REU_DEBUG, "No autoload\n");
}

triggerEndOfBlockIrq();
Expand Down Expand Up @@ -550,6 +568,9 @@ Reu::processEvent(EventID id)
// Perform a DMA cycle
bool success = doDma(id);

// Set or clear the END_OF_BLOCK_BIT
tlength == 1 ? SET_BIT(sr, 6) : CLR_BIT(sr, 6);

if (tlength == 1) {

finalizeDma(id);
Expand All @@ -569,9 +590,6 @@ Reu::processEvent(EventID id)
c64.cancel<SLOT_EXP>();
}
}

// Set or clear the END_OF_BLOCK_BIT
tlength == 1 ? SET_BIT(sr, 6) : CLR_BIT(sr, 6);
}

void
Expand All @@ -581,6 +599,8 @@ Reu::triggerEndOfBlockIrq()

sr |= 0x80;
cpu.pullDownIrqLine(INTSRC_EXP);

debug(REU_DEBUG, "IRQ triggered (sr = %02x)\n", sr);
}
}

Expand Down
2 changes: 1 addition & 1 deletion Emulator/Misc/RegressionTester/RegressionTester.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ RegressionTester::pokeDebugCart(u16 addr, u8 value)
}

void
RegressionTester::setWatchdog(isize cycle)
RegressionTester::setWatchdog(Cycle cycle)
{
if (cycle == 0) {

Expand Down
2 changes: 1 addition & 1 deletion Emulator/Misc/RegressionTester/RegressionTester.h
Original file line number Diff line number Diff line change
Expand Up @@ -141,7 +141,7 @@ class RegressionTester : public SubComponent {
void pokeDebugCart(u16 addr, u8 value);

// Starts (value > 0) or stops (value == 0) a watchdog timer
void setWatchdog(isize cycle);
void setWatchdog(Cycle cycle);
};

}

0 comments on commit 4739ea5

Please sign in to comment.