WorkLoad Optimize SOC (WLOS) Baseline

Simulation for matrix multiplication

cd ~/caravel-soc_fpga-lab/lab-wlos_baseline/testbench/counter_la_mm
source run_clean
source run_sim

Simulation for FIR

cd ~/caravel-soc_fpga-lab/lab-wlos_baseline/testbench/counter_la_fir
source run_clean
source run_sim

Simulation for qsort

cd ~/caravel-soc_fpga-lab/lab-wlos_baseline/testbench/counter_la_qs
source run_clean
source run_sim

Simulation for uart

cd ~/caravel-soc_fpga-lab/lab-wlos_baseline/testbench/uart
source run_clean
source run_sim

Verification with Vivado

Synthesis and Generate bitstream

cd ~/caravel-soc_fpga-lab/lab-wlos_baseline/vivado
source run_vivado