Update to release/1.13.0

Signed-off-by: ChipSec <[email protected]>
chipsec · Mar 28, 2024 · dc3b8b5 · dc3b8b5
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diff --git a/_sources/contribution/code-style-python.rst.txt b/_sources/contribution/code-style-python.rst.txt
@@ -77,7 +77,8 @@ If in doubt, follow the existing code style and formatting.
 
         # Good
         import sys
-        from chipsec.module_common import BaseModule, ModuleResult
+        from chipsec.module_common import BaseModule
+from chipsec.library.returncode import ModuleResult
 
         # Bad - using '*' and importing sys after local imports
         import *

diff --git a/_sources/development/Developing.rst.txt b/_sources/development/Developing.rst.txt
@@ -17,7 +17,7 @@ Most modules read some platform configuration and then pass or fail based on the
 
    .. code-block:: python
 
-    ble = self.cs.get_control('BiosLockEnable')
+    ble = self.cs.control.get('BiosLockEnable')
 
 3. React based on the status of the control:
 

diff --git a/_sources/development/Sample-Module-Code.rst.txt b/_sources/development/Sample-Module-Code.rst.txt
@@ -3,7 +3,8 @@ Sample module code template
 
 .. code-block:: python
 
-    from chipsec.module_common import BaseModule, ModuleResult
+    from chipsec.module_common import BaseModule
+    from chipsec.library.returncode import ModuleResult
 
     class ModuleClass(BaseModule):
         """Class name aligns with file name, eg ModuleClass.py"""

diff --git a/_sources/index.rst.txt b/_sources/index.rst.txt
@@ -1,10 +1,10 @@
-.. CHIPSEC documentation file, created by
+.. CHIPSEC 1.13.0 documentation file, created by
    sphinx-quickstart on Wed Mar 25 13:24:44 2015.
    You can adapt this file completely to your liking, but it should at least
    contain the root `toctree` directive.
 
-CHIPSEC
-=======
+CHIPSEC 1.13.0
+==============
 
 CHIPSEC is a framework for analyzing platform level security of
 hardware, devices, system firmware, low-level protection mechanisms, and

diff --git a/_sources/modules/chipsec.cfg.8086.adl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.adl.xml.rst.txt
@@ -0,0 +1,25 @@
+adl
+=======
+
+Path: chipsec\\cfg\\8086\\adl.xml
+
+
+CHIPSEC: Platform Security Assessment Framework
+Copyright (c) 2021-2022, Intel Corporation
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; Version 2.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+
+Contact information:
+[email protected]
+
diff --git a/_sources/modules/chipsec.cfg.8086.apl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.apl.xml.rst.txt
@@ -0,0 +1,9 @@
+apl
+=======
+
+Path: chipsec\\cfg\\8086\\apl.xml
+
+
+XML configuration for Apollo Lake based SoCs
+document id 334818/334819
+
diff --git a/_sources/modules/chipsec.cfg.8086.avn.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.avn.xml.rst.txt
@@ -0,0 +1,11 @@
+avn
+=======
+
+Path: chipsec\\cfg\\8086\\avn.xml
+
+
+XML configuration for Avoton based platforms
+
+* Intel(R) Atom(TM) Processor C2000 Product Family for Microserver, September 2014 
+  http://www.intel.com/content/www/us/en/processors/atom/atom-c2000-microserver-datasheet.html
+
diff --git a/_sources/modules/chipsec.cfg.8086.bdw.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.bdw.xml.rst.txt
@@ -0,0 +1,8 @@
+bdw
+=======
+
+Path: chipsec\\cfg\\8086\\bdw.xml
+
+
+XML configuration for Broadwell based platforms
+
diff --git a/_sources/modules/chipsec.cfg.8086.bdx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.bdx.xml.rst.txt
@@ -0,0 +1,13 @@
+bdx
+=======
+
+Path: chipsec\\cfg\\8086\\bdx.xml
+
+
+XML configuration file for Broadwell Server based platforms
+Intel (c) Xeon Processor E5 v4 Product Family datasheet Vol. 2
+Intel (c) Xeon Processor E7 v4 Product Family datasheet Vol. 2
+Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
+Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
+Intel (c) C610 Series Chipset and Intel (c) X99 Chipset Platform Controller Hub (PCH) datasheet
+
diff --git a/_sources/modules/chipsec.cfg.8086.byt.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.byt.xml.rst.txt
@@ -0,0 +1,11 @@
+byt
+=======
+
+Path: chipsec\\cfg\\8086\\byt.xml
+
+
+XML configuration for Bay Trail based platforms
+
+* Intel(R) Atom(TM) Processor E3800 Product Family Datasheet, May 2016, Revision 4.0
+  http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html
+
diff --git a/_sources/modules/chipsec.cfg.8086.cfl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.cfl.xml.rst.txt
@@ -0,0 +1,11 @@
+cfl
+=======
+
+Path: chipsec\\cfg\\8086\\cfl.xml
+
+
+XML configuration file for Coffee Lake
+
+* 8th Generation Intel(R) Processor Family for S-Processor Platforms
+  https://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
+
diff --git a/_sources/modules/chipsec.cfg.8086.cht.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.cht.xml.rst.txt
@@ -0,0 +1,14 @@
+cht
+=======
+
+Path: chipsec\\cfg\\8086\\cht.xml
+
+
+XML configuration for Cherry Trail and Braswell SoCs
+
+* Intel(R) Atom(TM) Processor Z8000 series datasheet
+  http://www.intel.com/content/www/us/en/processors/atom/atom-z8000-datasheet-vol-2.html
+
+* N-series Intel(R) Pentium(R) and Celeron(R) Processors Datasheet
+  http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-celeron-n-series-datasheet-vol-2.pdf
+
diff --git a/_sources/modules/chipsec.cfg.8086.cml.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.cml.xml.rst.txt
@@ -0,0 +1,6 @@
+cml
+=======
+
+Path: chipsec\\cfg\\8086\\cml.xml
+
+ XML configuration file for Comet Lake 
diff --git a/_sources/modules/chipsec.cfg.8086.common.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.common.xml.rst.txt
@@ -0,0 +1,8 @@
+common
+==========
+
+Path: chipsec\\cfg\\8086\\common.xml
+
+
+Common (default) XML platform configuration file
+
diff --git a/_sources/modules/chipsec.cfg.8086.dnv.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.dnv.xml.rst.txt
@@ -0,0 +1,12 @@
+dnv
+=======
+
+Path: chipsec\\cfg\\8086\\dnv.xml
+
+
+XML configuration file for Denverton
+
+* Intel Atom(R) Processor C3000 Product Family
+  https://www.intel.com/content/www/us/en/processors/atom/atom-technical-resources.html
+  337018-002
+
diff --git a/_sources/modules/chipsec.cfg.8086.ehl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.ehl.xml.rst.txt
@@ -0,0 +1,9 @@
+ehl
+=======
+
+Path: chipsec\\cfg\\8086\\ehl.xml
+
+
+XML configuration file for Elkhart Lake
+Document ID: 635255, 636112, 636722, 636723
+
diff --git a/_sources/modules/chipsec.cfg.8086.glk.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.glk.xml.rst.txt
@@ -0,0 +1,8 @@
+glk
+=======
+
+Path: chipsec\\cfg\\8086\\glk.xml
+
+ XML configuration for GLK
+  Document ID: 336561-001
+
diff --git a/_sources/modules/chipsec.cfg.8086.hsw.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.hsw.xml.rst.txt
@@ -0,0 +1,8 @@
+hsw
+=======
+
+Path: chipsec\\cfg\\8086\\hsw.xml
+
+
+XML configuration file for Haswell based platforms
+
diff --git a/_sources/modules/chipsec.cfg.8086.hsx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.hsx.xml.rst.txt
@@ -0,0 +1,13 @@
+hsx
+=======
+
+Path: chipsec\\cfg\\8086\\hsx.xml
+
+
+XML configuration file for Haswell Server based platforms
+Intel (c) Xeon Processor E5-1600/2400/2600/4600 v3 Product Family datasheet Vol. 2
+Intel (c) Xeon Processor E7-8800/4800 v3 Product Family datasheet Vol. 2
+Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
+Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
+Intel (c) C610 Series Chipset and Intel (c) X99 Chipset Platform Controller Hub (PCH) datasheet
+
diff --git a/_sources/modules/chipsec.cfg.8086.icl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.icl.xml.rst.txt
@@ -0,0 +1,6 @@
+icl
+=======
+
+Path: chipsec\\cfg\\8086\\icl.xml
+
+ XML configuration file for Ice Lake 
diff --git a/_sources/modules/chipsec.cfg.8086.icx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.icx.xml.rst.txt
@@ -0,0 +1,8 @@
+icx
+=======
+
+Path: chipsec\\cfg\\8086\\icx.xml
+
+
+XML configuration file for Icelake/Lewisburg Server
+
diff --git a/_sources/modules/chipsec.cfg.8086.iommu.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.iommu.xml.rst.txt
@@ -0,0 +1,11 @@
+iommu
+=========
+
+Path: chipsec\\cfg\\8086\\iommu.xml
+
+
+XML configuration file for Intel Virtualization Technology for Directed I/O (VT-d)
+
+* Section 10 of Intel Virtualization Technology for Directed I/O
+  http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
+
diff --git a/_sources/modules/chipsec.cfg.8086.ivb.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.ivb.xml.rst.txt
@@ -0,0 +1,8 @@
+ivb
+=======
+
+Path: chipsec\\cfg\\8086\\ivb.xml
+
+
+XML configuration for IvyBridge based platforms
+
diff --git a/_sources/modules/chipsec.cfg.8086.ivt.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.ivt.xml.rst.txt
@@ -0,0 +1,8 @@
+ivt
+=======
+
+Path: chipsec\\cfg\\8086\\ivt.xml
+
+
+XML configuration file for Ivytown (Ivy Bridge-E) based platforms
+
diff --git a/_sources/modules/chipsec.cfg.8086.jkt.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.jkt.xml.rst.txt
@@ -0,0 +1,8 @@
+jkt
+=======
+
+Path: chipsec\\cfg\\8086\\jkt.xml
+
+
+XML configuration file for Jaketown (Sandy Bridge-E) based platforms
+
diff --git a/_sources/modules/chipsec.cfg.8086.kbl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.kbl.xml.rst.txt
@@ -0,0 +1,14 @@
+kbl
+=======
+
+Path: chipsec\\cfg\\8086\\kbl.xml
+
+
+XML configuration file for Kaby Lake based platforms
+
+http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
+
+* 7th Generation Intel(R) Processor Families for U/Y-Platforms
+
+* 7th Generation Intel(R) Processor Families I/O for U/Y-Platforms
+
diff --git a/_sources/modules/chipsec.cfg.8086.pch_1xx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_1xx.xml.rst.txt
@@ -0,0 +1,30 @@
+pch_1xx
+===========
+
+Path: chipsec\\cfg\\8086\\pch_1xx.xml
+
+
+XML configuration file for 100 series PCH based platforms
+
+CHIPSEC: Platform Security Assessment Framework
+Copyright (c) 2020-2021, Intel Corporation
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; Version 2.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+
+Contact information:
+[email protected]
+
+* Intel(R) 100 Series Chipset Family Platform Controller Hub (PCH)
+  http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
+
diff --git a/_sources/modules/chipsec.cfg.8086.pch_2xx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_2xx.xml.rst.txt
@@ -0,0 +1,11 @@
+pch_2xx
+===========
+
+Path: chipsec\\cfg\\8086\\pch_2xx.xml
+
+
+XML configuration file for 200 series PCH based platforms
+
+* Intel(R) 200 Series Chipset Family Platform Controller Hub (PCH)
+  http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
+
diff --git a/_sources/modules/chipsec.cfg.8086.pch_3xx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_3xx.xml.rst.txt
@@ -0,0 +1,10 @@
+pch_3xx
+===========
+
+Path: chipsec\\cfg\\8086\\pch_3xx.xml
+
+
+XML configuration file for the 300 series PCH
+https://www.intel.com/content/www/us/en/products/docs/chipsets/300-series-chipset-pch-datasheet-vol-2.html
+337348-001
+
diff --git a/_sources/modules/chipsec.cfg.8086.pch_3xxlp.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_3xxlp.xml.rst.txt
@@ -0,0 +1,10 @@
+pch_3xxlp
+=============
+
+Path: chipsec\\cfg\\8086\\pch_3xxlp.xml
+
+
+XML configuration file for the 300 series LP (U/Y) PCH
+https://www.intel.com/content/www/us/en/products/docs/processors/core/7th-and-8th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-2.html
+334659-005
+
diff --git a/_sources/modules/chipsec.cfg.8086.pch_3xxop.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_3xxop.xml.rst.txt
@@ -0,0 +1,10 @@
+pch_3xxop
+=============
+
+Path: chipsec\\cfg\\8086\\pch_3xxop.xml
+
+
+XML configuration file for the 300 series On Package PCH
+https://www.intel.com/content/www/us/en/products/docs/chipsets/300-series-chipset-on-package-pch-datasheet-vol-2.html
+337868-002
+
diff --git a/_sources/modules/chipsec.cfg.8086.pch_495.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_495.xml.rst.txt
@@ -0,0 +1,8 @@
+pch_495
+===========
+
+Path: chipsec\\cfg\\8086\\pch_495.xml
+
+
+XML configuration file for the 495 series PCH
+
diff --git a/_sources/modules/chipsec.cfg.8086.pch_4xx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_4xx.xml.rst.txt
@@ -0,0 +1,8 @@
+pch_4xx
+===========
+
+Path: chipsec\\cfg\\8086\\pch_4xx.xml
+
+
+  XML configuration file for 4XX pch
+
diff --git a/_sources/modules/chipsec.cfg.8086.pch_4xxh.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_4xxh.xml.rst.txt
@@ -0,0 +1,8 @@
+pch_4xxh
+============
+
+Path: chipsec\\cfg\\8086\\pch_4xxh.xml
+
+
+  XML configuration file 4xxH PCH 620855
+