Resetting a RocketTile/Core - Simulating a context switch

[ggeier]

Hi everybody,
I am trying to run tests programs on a RocketTile via Verilator simulation. How do I reset the architectural state properly e.g. as a context switch would? I would prefer not to start Verilator again for each run and I want to keep the microarchitectural state which would not be affected by a switch.
Possibilities that I thought of:

• Would it be sufficient to leave the reset port high for a couple of cycles? How many? Would this variant reset only the architectural state or also e.g. some buffers?
• Could I also just reset certain registers manually? For example by setting them via the Verilator interface to 0.