DCache errors.bus.bits is qualified with grantIsCached. why?

[bonannojj]

rocket-chip/src/main/scala/rocket/DCache.scala

Line 1104 in bf5742b

io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U)

Why is this address qualified with grantIsCached? This means memory mapped io errors, while still indicating the error to the beu, would report 0 for the physical address.

Could/should this qualification be removed?
s2_req.addr seems valid to use even when grantIsCached is 0.

[bonannojj]

Is it perhaps due to the nonblocking nature of MMIO uncached requests that could mean that s2_req.addr is not guaranteed to be valid at the time of detecting the error? In which case it might be necessary to get it from the appropriate uncachedreqs_*_addr.