try add TEQ instructions

cea-sec · Apr 28, 2019 · 73bf3b9 · 73bf3b9
1 parent 41c661c
commit 73bf3b9
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/miasm/arch/arm/arch.py b/miasm/arch/arm/arch.py
@@ -1439,6 +1439,7 @@ def encode(self):
 imm12_off = bs(l=12, fname="imm")
 
 imm2_noarg = bs(l=2, fname="imm")
+imm3_noarg = bs(l=3, fname="imm3")
 imm4_noarg = bs(l=4, fname="imm4")
 
 
@@ -2431,6 +2432,7 @@ class arm_sp(arm_reg):
 armtop("addsubi", [bs('000111'),  bs_addsub_name, off3, rsl, rdl], [rdl, rsl, off3])
 armtop("mcas", [bs('001'), bs_mov_cmp_add_sub_name, rnl, off8])
 armtop("alu", [bs('010000'), bs_alu_name, rsl, rdl], [rdl, rsl])
+
   # should not be used ??
 armtop("hiregop00", [bs('010001'), bs_hiregop_name, bs('00'), rsl, rdl], [rdl, rsl])
 armtop("hiregop01", [bs('010001'), bs_hiregop_name, bs('01'), rsh, rdl], [rdl, rsh])
@@ -3370,3 +3372,6 @@ def check_fbits(self, v):
 armtop("dsb",  [bs('111100111011'), bs('1111'), bs('1000'), bs('1111'), bs('0100'), barrier_option])
 
 armtop("adr", [bs('11110'), imm12_1, bs('100000'), bs('1111'), bs('0'), imm12_3, rd, imm12_8_t4], [rd, imm12_8_t4])
+
+
+armtop("teq", [bs('111010101001'), rn_noarg, bs('0'), imm3_noarg, bs('1111'), imm2_noarg, imm_stype, rm_noarg])