[cdm16e] Fix swpw and swpb mnemonics in microcode

cdm-processors · Feb 12, 2024 · 00bc440 · 00bc440
1 parent 4581ce1
commit 00bc440
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/logisim/cdm16e/microcode/cdm16e_decoder.def b/logisim/cdm16e/microcode/cdm16e_decoder.def
@@ -130,11 +130,11 @@ stssp:          r_asrtD
 move:           r_asrt0, alu_asrtD, r_latch, ps_latch_flags
 2op_1:
 
-sww:            mem, data, read, word, r_asrt0;
+swpw:           mem, data, read, word, r_asrt0;
                 mem, data, word, r_asrt0, r_asrtD;
                 r_latch
 
-swb:            mem, data, read, r_asrt0;
+swpb:           mem, data, read, r_asrt0;
                 mem, data, r_asrt0, r_asrtD;
                 r_latch
 

diff --git a/logisim/cdm16e/microcode/cdm16e_decoder_exc.def b/logisim/cdm16e/microcode/cdm16e_decoder_exc.def
@@ -153,11 +153,11 @@ move:           r_asrt0, alu_asrtD; # r_latch, ps_latch_flags
                 pc_inc
 2op_1:
 
-sww:            mem, data, read, word, r_asrt0;
+swpw:           mem, data, read, word, r_asrt0;
                 mem, data, word, r_asrt0, r_asrtD;
                 pc_inc # r_latch
 
-swb:            mem, data, read, r_asrt0;
+swpb:           mem, data, read, r_asrt0;
                 mem, data, r_asrt0, r_asrtD;
                 pc_inc # r_latch