Xtensa fixes

- fix MCExpr - fix Xtensa_add_cs_detail - add `add_cs_detail` - add `MCExpr *MCOperand_getExpr(const MCOperand *MC)` `void printExpr(const MCExpr *E, SStream *O)` autosync fix - fix StreamOperation.py - replace `report_fatal_error` with `CS_ASSERT` - fix patch StreamOperation.py - replace `assert` with `CS_ASSERT` - fix AddCSDetail.py - fix QualifiedIdentifier
capstone-engine · Sep 3, 2024 · 9fa09bb · 9fa09bb
1 parent 8a16d09
commit 9fa09bb
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Showing 49 changed files with 1,108 additions and 162 deletions.
diff --git a/MCInst.c b/MCInst.c
@@ -165,6 +165,12 @@ void MCOperand_setFPImm(MCOperand *op, double Val)
 	op->FPImmVal = Val;
 }
 
+MCExpr *MCOperand_getExpr(const MCOperand *MC)
+{
+	assert(0 && "unimplemented expr");
+	return NULL;
+}
+
 MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
 {
 	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);

diff --git a/MCInst.h b/MCInst.h
@@ -26,7 +26,7 @@
 typedef struct MCInst MCInst;
 typedef struct cs_struct cs_struct;
 typedef struct MCOperand MCOperand;
-typedef unsigned MCRegister;
+typedef void MCExpr;
 
 /// MCOperand - Instances of this class represent operands of the MCInst class.
 /// This is a simple discriminated union.
@@ -81,6 +81,8 @@ const MCInst *MCOperand_getInst(const MCOperand *op);
 
 void MCOperand_setInst(MCOperand *op, const MCInst *Val);
 
+MCExpr *MCOperand_getExpr(const MCOperand *MC);
+
 // create Reg operand in the next slot
 void MCOperand_CreateReg0(MCInst *inst, unsigned Reg);
 

diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h
@@ -20,11 +20,13 @@
 #define CS_LLVM_MC_MCREGISTERINFO_H
 
 #include "capstone/platform.h"
+#include "SStream.h"
 
 /// An unsigned integer type large enough to represent all physical registers,
 /// but not necessarily virtual registers.
 typedef int16_t MCPhysReg;
 typedef const MCPhysReg* iterator;
+typedef uint16_t MCRegister;
 
 typedef struct MCRegisterClass2 {
 	iterator RegsBegin;

diff --git a/Mapping.c b/Mapping.c
@@ -339,6 +339,7 @@ DEFINE_get_detail_op(alpha, Alpha);
 DEFINE_get_detail_op(hppa, HPPA);
 DEFINE_get_detail_op(loongarch, LoongArch);
 DEFINE_get_detail_op(riscv, RISCV);
+DEFINE_get_detail_op(xtensa, Xtensa);
 
 /// Returns true if for this architecture the
 /// alias operands should be filled.

diff --git a/Mapping.h b/Mapping.h
@@ -139,6 +139,7 @@ DECL_get_detail_op(alpha, Alpha);
 DECL_get_detail_op(hppa, HPPA);
 DECL_get_detail_op(loongarch, LoongArch);
 DECL_get_detail_op(riscv, RISCV);
+DECL_get_detail_op(xtensa, Xtensa);
 
 /// Increments the detail->arch.op_count by one.
 #define DEFINE_inc_detail_op_count(arch, ARCH) \
@@ -201,6 +202,7 @@ DEFINE_get_arch_detail(alpha, Alpha);
 DEFINE_get_arch_detail(hppa, HPPA);
 DEFINE_get_arch_detail(loongarch, LoongArch);
 DEFINE_get_arch_detail(riscv, RISCV);
+DEFINE_get_arch_detail(xtensa, Xtensa);
 
 static inline bool detail_is_set(const MCInst *MI)
 {

diff --git a/arch/Xtensa/XtensaDisassembler.c b/arch/Xtensa/XtensaDisassembler.c
@@ -71,7 +71,7 @@ static DecodeStatus DecodeSRRegisterClass(MCInst *Inst, uint64_t RegNo,
 	if (RegNo > 255)
 		return MCDisassembler_Fail;
 
-	for (unsigned i = 0; i < sizeof(SRDecoderTable); i += 2) {
+	for (unsigned i = 0; i + 1 < sizeof(SRDecoderTable); i += 2) {
 		if (SRDecoderTable[i + 1] == RegNo) {
 			unsigned Reg = SRDecoderTable[i];
 			MCOperand_CreateReg0(Inst, (Reg));
@@ -95,13 +95,15 @@ static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
 static DecodeStatus decodeCallOperand(MCInst *Inst, uint64_t Imm,
 				      int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 18)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 2), 20)));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus decodeJumpOperand(MCInst *Inst, uint64_t Imm,
 				      int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 18)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 18)));
 	return MCDisassembler_Success;
 }
@@ -114,14 +116,14 @@ static DecodeStatus decodeBranchOperand(MCInst *Inst, uint64_t Imm,
 	case Xtensa_BGEZ:
 	case Xtensa_BLTZ:
 	case Xtensa_BNEZ:
-
+		CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate");
 		if (!tryAddingSymbolicOperand(
 			    SignExtend64((Imm), 12) + 4 + Address, true,
 			    Address, 0, 3, Inst, Decoder))
 			MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 12)));
 		break;
 	default:
-
+		CS_ASSERT(CONCAT(isUInt, 8)(Imm) && "Invalid immediate");
 		if (!tryAddingSymbolicOperand(
 			    SignExtend64((Imm), 8) + 4 + Address, true, Address,
 			    0, 3, Inst, Decoder))
@@ -133,6 +135,7 @@ static DecodeStatus decodeBranchOperand(MCInst *Inst, uint64_t Imm,
 static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm,
 				      int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 16)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(
 		Inst,
 		(SignExtend64(((Imm << 2) + 0x40000 + (Address & 0x3)), 17)));
@@ -142,48 +145,55 @@ static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm,
 static DecodeStatus decodeImm8Operand(MCInst *Inst, uint64_t Imm,
 				      int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 8)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 8)));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus decodeImm8_sh8Operand(MCInst *Inst, uint64_t Imm,
 					  int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 8)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 8), 16)));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus decodeImm12Operand(MCInst *Inst, uint64_t Imm,
 				       int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 12)));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus decodeUimm4Operand(MCInst *Inst, uint64_t Imm,
 				       int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (Imm));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus decodeUimm5Operand(MCInst *Inst, uint64_t Imm,
 				       int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 5)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (Imm));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus decodeImm1_16Operand(MCInst *Inst, uint64_t Imm,
 					 int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (Imm + 1));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus decodeShimm1_31Operand(MCInst *Inst, uint64_t Imm,
 					   int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 5)(Imm) && "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (32 - Imm));
 	return MCDisassembler_Success;
 }
@@ -193,6 +203,8 @@ static int64_t TableB4const[16] = { -1, 1,  2,	3,  4,	5,  6,	 7,
 static DecodeStatus decodeB4constOperand(MCInst *Inst, uint64_t Imm,
 					 int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate");
+
 	MCOperand_CreateImm0(Inst, (TableB4const[Imm]));
 	return MCDisassembler_Success;
 }
@@ -202,13 +214,16 @@ static int64_t TableB4constu[16] = { 32768, 65536, 2,  3,  4,  5,  6,	7,
 static DecodeStatus decodeB4constuOperand(MCInst *Inst, uint64_t Imm,
 					  int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate");
+
 	MCOperand_CreateImm0(Inst, (TableB4constu[Imm]));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus decodeMem8Operand(MCInst *Inst, uint64_t Imm,
 				      int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate");
 	DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
 	MCOperand_CreateImm0(Inst, ((Imm >> 4) & 0xff));
 	return MCDisassembler_Success;
@@ -217,6 +232,7 @@ static DecodeStatus decodeMem8Operand(MCInst *Inst, uint64_t Imm,
 static DecodeStatus decodeMem16Operand(MCInst *Inst, uint64_t Imm,
 				       int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate");
 	DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
 	MCOperand_CreateImm0(Inst, ((Imm >> 3) & 0x1fe));
 	return MCDisassembler_Success;
@@ -225,6 +241,7 @@ static DecodeStatus decodeMem16Operand(MCInst *Inst, uint64_t Imm,
 static DecodeStatus decodeMem32Operand(MCInst *Inst, uint64_t Imm,
 				       int64_t Address, const void *Decoder)
 {
+	CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate");
 	DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
 	MCOperand_CreateImm0(Inst, ((Imm >> 2) & 0x3fc));
 	return MCDisassembler_Success;

diff --git a/arch/Xtensa/XtensaDisassembler.h b/arch/Xtensa/XtensaDisassembler.h
@@ -1,3 +1,6 @@
+/* Capstone Disassembly Engine */
+/* By billow <[email protected]>, 2024 */
+
 #ifndef XTENSA_DISASSEMBLER_H
 #define XTENSA_DISASSEMBLER_H