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Fix shadowing warnings.
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@Rot127
Rot127 committed Apr 10, 2024
1 parent a5ea0f9 commit 66cc6d3
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Showing 9 changed files with 46 additions and 50 deletions.
2 changes: 1 addition & 1 deletion .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -131,7 +131,7 @@ fuzz_bindisasm
fuzz_disasm
fuzz_decode_platform
capstone_get_setup
suite/fuzz/
suite/fuzz/corpus
suite/cstest/cmocka/

*.s
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16 changes: 8 additions & 8 deletions arch/AArch64/AArch64Disassembler.c
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Expand Up @@ -360,25 +360,25 @@ static DecodeStatus getInstruction(csh handle, const uint8_t *Bytes, size_t Byte
// For Scalable Matrix Extension (SME) instructions that have an
// implicit operand for the accumulator (ZA) or implicit immediate zero
// which isn't encoded, manually insert operand.
for (unsigned i = 0; i < Desc.NumOperands; i++) {
if (Desc.OpInfo[i].OperandType == MCOI_OPERAND_REGISTER) {
switch (Desc.OpInfo[i].RegClass) {
for (unsigned j = 0; j < Desc.NumOperands; j++) {
if (Desc.OpInfo[j].OperandType == MCOI_OPERAND_REGISTER) {
switch (Desc.OpInfo[j].RegClass) {
default:
break;
case AArch64_MPRRegClassID:
MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, AArch64_ZA));
MCInst_insert0(MI, j, MCOperand_CreateReg1(MI, AArch64_ZA));
break;
case AArch64_MPR8RegClassID:
MCInst_insert0(MI, i,
MCInst_insert0(MI, j,
MCOperand_CreateReg1(MI, AArch64_ZAB0));
break;
case AArch64_ZTRRegClassID:
MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, AArch64_ZT0));
MCInst_insert0(MI, j, MCOperand_CreateReg1(MI, AArch64_ZT0));
break;
}
} else if (Desc.OpInfo[i].OperandType ==
} else if (Desc.OpInfo[j].OperandType ==
AArch64_OP_IMPLICIT_IMM_0) {
MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, 0));
MCInst_insert0(MI, j, MCOperand_CreateImm1(MI, 0));
}
}

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2 changes: 1 addition & 1 deletion arch/AArch64/AArch64InstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1358,7 +1358,7 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
unsigned Reg = MCOperand_getReg(Op);
printRegName(O, Reg);
} else if (MCOperand_isImm(Op)) {
MCOperand *Op = MCInst_getOperand(MI, (OpNo));
Op = MCInst_getOperand(MI, (OpNo));
SStream_concat(O, "%s", markup("<imm:"));
printInt64Bang(O, MCOperand_getImm(Op));
SStream_concat0(O, markup(">"));
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2 changes: 1 addition & 1 deletion arch/ARM/ARMDisassembler.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2082,7 +2082,7 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
unsigned amt = fieldFromInstruction_4(Insn, 7, 5);
if (Opc == ARM_AM_ror && amt == 0)
Opc = ARM_AM_rrx;
unsigned imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode);
imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode);

MCOperand_CreateImm0(Inst, (imm));
} else {
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58 changes: 29 additions & 29 deletions arch/ARM/ARMMapping.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1354,11 +1354,11 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group,
MCInst_getOpVal(MI, OpNum) + 1);
break;
case ARM_OP_GROUP_RotImmOperand: {
unsigned Imm = MCInst_getOpVal(MI, OpNum);
if (Imm == 0)
unsigned RotImm = MCInst_getOpVal(MI, OpNum);
if (RotImm == 0)
return;
ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ROR;
ARM_get_detail_op(MI, -1)->shift.value = Imm * 8;
ARM_get_detail_op(MI, -1)->shift.value = RotImm * 8;
break;
}
case ARM_OP_GROUP_FBits16:
Expand Down Expand Up @@ -1390,16 +1390,16 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group,
break;
}
case ARM_OP_GROUP_PostIdxImm8Operand: {
unsigned Imm = MCInst_getOpVal(MI, OpNum);
bool sub = !(Imm & 256);
ARM_set_detail_op_mem_offset(MI, OpNum, (Imm & 0xff), sub);
unsigned Imm8 = MCInst_getOpVal(MI, OpNum);
bool sub = !(Imm8 & 256);
ARM_set_detail_op_mem_offset(MI, OpNum, (Imm8 & 0xff), sub);
ARM_get_detail(MI)->post_index = true;
break;
}
case ARM_OP_GROUP_PostIdxImm8s4Operand: {
unsigned Imm = MCInst_getOpVal(MI, OpNum);
bool sub = !(Imm & 256);
ARM_set_detail_op_mem_offset(MI, OpNum, (Imm & 0xff) << 2, sub);
unsigned Imm8s = MCInst_getOpVal(MI, OpNum);
bool sub = !(Imm8s & 256);
ARM_set_detail_op_mem_offset(MI, OpNum, (Imm8s & 0xff) << 2, sub);
ARM_get_detail(MI)->post_index = true;
break;
}
Expand Down Expand Up @@ -1569,36 +1569,36 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group,
ARM_set_mem_access(MI, true);
ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
MCInst_getOpVal(MI, OpNum));
int64_t Imm = MCInst_getOpVal(MI, OpNum + 1);
if (Imm)
int64_t Imm0_1024s4 = MCInst_getOpVal(MI, OpNum + 1);
if (Imm0_1024s4)
ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0,
Imm * 4);
Imm0_1024s4 * 4);
ARM_set_mem_access(MI, false);
break;
case ARM_OP_GROUP_PKHLSLShiftImm: {
unsigned Imm = MCInst_getOpVal(MI, OpNum);
if (Imm == 0)
unsigned ShiftImm = MCInst_getOpVal(MI, OpNum);
if (ShiftImm == 0)
return;
ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_LSL;
ARM_get_detail_op(MI, -1)->shift.value = Imm;
ARM_get_detail_op(MI, -1)->shift.value = ShiftImm;
break;
}
case ARM_OP_GROUP_PKHASRShiftImm: {
unsigned Imm = MCInst_getOpVal(MI, OpNum);
if (Imm == 0)
Imm = 32;
unsigned RShiftImm = MCInst_getOpVal(MI, OpNum);
if (RShiftImm == 0)
RShiftImm = 32;
ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ASR;
ARM_get_detail_op(MI, -1)->shift.value = Imm;
ARM_get_detail_op(MI, -1)->shift.value = RShiftImm;
break;
}
case ARM_OP_GROUP_ThumbS4ImmOperand:
ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM,
MCInst_getOpVal(MI, OpNum) * 4);
break;
case ARM_OP_GROUP_ThumbSRImm: {
unsigned Imm = MCInst_getOpVal(MI, OpNum);
unsigned SRImm = MCInst_getOpVal(MI, OpNum);
ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM,
Imm == 0 ? 32 : Imm);
SRImm == 0 ? 32 : SRImm);
break;
}
case ARM_OP_GROUP_BitfieldInvMaskImmOperand: {
Expand All @@ -1610,8 +1610,8 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group,
break;
}
case ARM_OP_GROUP_CPSIMod: {
unsigned Imm = MCInst_getOpVal(MI, OpNum);
ARM_get_detail(MI)->cps_mode = Imm;
unsigned Mode = MCInst_getOpVal(MI, OpNum);
ARM_get_detail(MI)->cps_mode = Mode;
break;
}
case ARM_OP_GROUP_CPSIFlag: {
Expand Down Expand Up @@ -1730,10 +1730,10 @@ static void add_cs_detail_template_1(MCInst *MI, arm_op_group op_group,
ARM_set_mem_access(MI, true);
ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
MCInst_getOpVal(MI, OpNum));
int32_t Imm = MCInst_getOpVal(MI, OpNum + 1);
if (Imm == INT32_MIN)
Imm = 0;
ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, Imm);
int32_t Imm8 = MCInst_getOpVal(MI, OpNum + 1);
if (Imm8 == INT32_MIN)
Imm8 = 0;
ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, Imm8);
if (AlwaysPrintImm0)
map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum));

Expand Down Expand Up @@ -1864,8 +1864,8 @@ static void add_cs_detail_template_2(MCInst *MI, arm_op_group op_group,
case ARM_OP_GROUP_ComplexRotationOp_180_90: {
unsigned Angle = temp_arg_0;
unsigned Remainder = temp_arg_1;
unsigned Imm = (MCInst_getOpVal(MI, OpNum) * Angle) + Remainder;
ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Imm);
unsigned Rotation = (MCInst_getOpVal(MI, OpNum) * Angle) + Remainder;
ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Rotation);
break;
}
}
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2 changes: 1 addition & 1 deletion arch/HPPA/HPPADisassembler.c
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Expand Up @@ -2776,7 +2776,7 @@ static void fill_copr_mods(uint32_t insn, uint32_t uid, uint32_t class,
push_str_modifier(hppa_ext, "n");
}
} else {
uint32_t uid = get_insn_field(insn, 23, 25);
uid = get_insn_field(insn, 23, 25);
uint32_t sop = (get_insn_field(insn, 6, 22) << 5) |
get_insn_field(insn, 27, 31);
push_int_modifier(hppa_ext, uid);
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4 changes: 1 addition & 3 deletions arch/M68K/M68KDisassembler.c
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Expand Up @@ -1944,9 +1944,7 @@ static void d68020_cpgen(m68k_info *info)
// special handling for fmovecr

if (BITFIELD(info->ir, 5, 0) == 0 && BITFIELD(next, 15, 10) == 0x17) {
cs_m68k_op* op0;
cs_m68k_op* op1;
cs_m68k* ext = build_init_op(info, M68K_INS_FMOVECR, 2, 0);
ext = build_init_op(info, M68K_INS_FMOVECR, 2, 0);

op0 = &ext->operands[0];
op1 = &ext->operands[1];
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2 changes: 0 additions & 2 deletions cstool/cstool.c
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Expand Up @@ -645,8 +645,6 @@ int main(int argc, char **argv)

count = cs_disasm(handle, assembly, size, address, 0, &insn);
if (count > 0) {
size_t i;

for (i = 0; i < count; i++) {
int j;

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8 changes: 4 additions & 4 deletions suite/fuzz/fuzz_disasm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -60,12 +60,12 @@ int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
unsigned int n;

for (j = 0; j < count; j++) {
cs_insn *i = &(all_insn[j]);
cs_insn *insn = &(all_insn[j]);
fprintf(outfile, "0x%"PRIx64":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
i->address, i->mnemonic, i->op_str,
i->id, cs_insn_name(handle, i->id));
insn->address, insn->mnemonic, insn->op_str,
insn->id, cs_insn_name(handle, insn->id));

detail = i->detail;
detail = insn->detail;

if (detail->regs_read_count > 0) {
fprintf(outfile, "\tImplicit registers read: ");
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