Skip to content

Commit

Permalink
Fix tests: 'Vector arra...' to 'operands[x].vas'
Browse files Browse the repository at this point in the history
  • Loading branch information
@Rot127
Rot127 committed May 21, 2024
1 parent a843421 commit 636755f
Show file tree
Hide file tree
Showing 2 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion suite/cstest/issues.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@

!# issue 1924 SME Index instruction alias printing is not always valid
!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
0x02,0x00,0x9f,0xe0 == ld1w {za0h.s[w12, 2]}, p0/z, [x0] ; op_count: 2 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za0.s ; operands[0].sme.slice_reg: w12 ; operands[0].sme.slice_offset: 2 ; operands[0].sme.is_vertical: false ; operands[0].access: READ ; operands[0].vas: 0x20 ; operands[0].vector_index: 0 ; operands[1].type: MEM ; operands[1].mem.base: REG = p0 ; operands[1].mem.index: REG = x0 ; operands[1].access: READ ; operands[0].vector_index: 0 ; Registers read: p0 x0 ; Groups: HasSME
0x02,0x00,0x9f,0xe0 == ld1w {za0h.s[w12, 2]}, p0/z, [x0] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.mx.tile: za0.s ; operands[0].sme.mx.slice_reg: w12 ; operands[0].sme.mx.slice_offset: 2 ; operands[0].sme.mx.is_vertical: false ; operands[0].access: WRITE ; operands[0].vas: 0x20 ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p0 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x0 ; operands[2].access: READ ; Registers read: za0.s w12 p0 x0 ; Groups: HasSME

!# issue 1912 PPC register name
!# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, None
Expand Down
6 changes: 3 additions & 3 deletions tests/cs_details/issue.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -206,12 +206,12 @@

!# issue 0 AArch64 operands
!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
0xc0,0x08,0x9f,0xe0 == ld1w {za0h.s[w12, 0]}, p2/z, [x6] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.mx.tile: za0.s ; operands[0].sme.mx.slice_reg: w12 ; operands[0].sme.mx.slice_offset: 0 ; operands[0].sme.mx.is_vertical: false ; operands[0].access: WRITE ; Vector Arrangement Specifier: 0x20 ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x6 ; operands[2].access: READ ; Registers read: za0.s w12 p2 x6 ; Groups: HasSME
0xc0,0x08,0x9f,0xe0 == ld1w {za0h.s[w12, 0]}, p2/z, [x6] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.mx.tile: za0.s ; operands[0].sme.mx.slice_reg: w12 ; operands[0].sme.mx.slice_offset: 0 ; operands[0].sme.mx.is_vertical: false ; operands[0].access: WRITE ; operands[0].vas: 0x20 ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x6 ; operands[2].access: READ ; Registers read: za0.s w12 p2 x6 ; Groups: HasSME

!# issue 0 AArch64 operands
!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
0x41,0x31,0xa2,0xe0 == st1w {za0h.s[w13, 1]}, p4, [x10, x2, lsl #2] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.mx.tile: za0.s ; operands[0].sme.mx.slice_reg: w13 ; operands[0].sme.mx.slice_offset: 1 ; operands[0].sme.mx.is_vertical: false ; operands[0].access: READ ; Vector Arrangement Specifier: 0x20 ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p4 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x10 ; operands[2].mem.index: REG = x2 ; operands[2].access: WRITE ; Shift: type = 1, value = 2 ; Registers read: za0.s w13 p4 x10 x2 ; Groups: HasSME
0x41,0x31,0xa2,0xe0 == st1w {za0h.s[w13, 1]}, p4, [x10, x2, lsl #2] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.mx.tile: za0.s ; operands[0].sme.mx.slice_reg: w13 ; operands[0].sme.mx.slice_offset: 1 ; operands[0].sme.mx.is_vertical: false ; operands[0].access: READ ; operands[0].vas: 0x20 ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p4 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x10 ; operands[2].mem.index: REG = x2 ; operands[2].access: WRITE ; Shift: type = 1, value = 2 ; Registers read: za0.s w13 p4 x10 x2 ; Groups: HasSME

!# issue 0 AArch64 operands
!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
0x67,0x44,0x71,0x25 == psel p7, p1, p3.s[w13, 1] ; op_count: 3 ; operands[0].type: SME_PRED ; operands[0].sme.pred.reg: p7 ; operands[0].access: WRITE ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p1 ; operands[1].access: READ ; operands[2].type: SME_PRED ; operands[2].sme.pred.reg: p3 ; operands[2].sme.pred.vec_select: w13 ; operands[2].sme.pred.index: 1 ; operands[2].access: READ ; Vector Arrangement Specifier: 0x20 ; Registers read: p7 p1 p3 w13 ; Groups: HasSVE2p1_or_HasSME
0x67,0x44,0x71,0x25 == psel p7, p1, p3.s[w13, 1] ; op_count: 3 ; operands[0].type: SME_PRED ; operands[0].sme.pred.reg: p7 ; operands[0].access: WRITE ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p1 ; operands[1].access: READ ; operands[2].type: SME_PRED ; operands[2].sme.pred.reg: p3 ; operands[2].sme.pred.vec_select: w13 ; operands[2].sme.pred.index: 1 ; operands[2].access: READ ; operands[2].vas: 0x20 ; Registers read: p7 p1 p3 w13 ; Groups: HasSVE2p1_or_HasSME

0 comments on commit 636755f

Please sign in to comment.