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Fix: Same printing format of detail for cstool, test_ and test_*.py
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@Rot127
Rot127 committed Nov 3, 2023
1 parent 75602e3 commit 09321bd
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Showing 2 changed files with 137 additions and 49 deletions.
11 changes: 5 additions & 6 deletions bindings/python/test_aarch64.py
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Original file line number Diff line number Diff line change
Expand Up @@ -47,14 +47,16 @@ def print_insn_detail(insn):
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x_32(i.mem.disp)))
if insn.post_index:
print("\t\t\tpost-indexed: true");
if i.type == AArch64_OP_SME_MATRIX:
print("\t\toperands[%u].type: SME_MATRIX\n" % (c))
print("\t\toperands[%u].sme.type: %d\n" % (c, i.sme.type))

if i.sme.tile != AArch64_REG_INVALID:
print("\t\toperands[%u].sme.tile: %s\n" % (c, cs_reg_name(handle, i.sme.tile)))
print("\t\toperands[%u].sme.tile: %s\n" % (c, insn.reg_name(i.sme.tile)))
if i.sme.slice_reg != AArch64_REG_INVALID:
print("\t\toperands[%u].sme.slice_reg: %s\n" % (c, cs_reg_name(handle, i.sme.slice_reg)))
print("\t\toperands[%u].sme.slice_reg: %s\n" % (c, insn.reg_name(i.sme.slice_reg)))
if i.sme.slice_offset.imm != -1 or i.sme.slice_offset.imm_range.first != -1:
print("\t\toperands[%u].sme.slice_offset: " % (c))
if i.sme.has_range_offset:
Expand Down Expand Up @@ -137,10 +139,7 @@ def print_insn_detail(insn):
print("\t\t\tVector Index: %u" % i.vector_index)

if insn.writeback:
if insn.post_index:
print("\tWrite-back: Post")
else:
print("\tWrite-back: Pre")
print("\tWrite-back: True")

if not insn.cc in [AArch64CC_AL, AArch64CC_Invalid]:
print("\tCode-condition: %u" % insn.cc)
Expand Down
175 changes: 132 additions & 43 deletions tests/test_aarch64.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,59 +49,149 @@ static void print_insn_detail(cs_insn *ins)
for (i = 0; i < aarch64->op_count; i++) {
cs_aarch64_op *op = &(aarch64->operands[i]);
switch(op->type) {
default:
break;
case AArch64_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
break;
case AArch64_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
break;
case AArch64_OP_FP:
default:
break;
case AArch64_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
break;
case AArch64_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
break;
case AArch64_OP_FP:
#if defined(_KERNEL_MODE)
// Issue #681: Windows kernel does not support formatting float point
printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i);
// Issue #681: Windows kernel does not support formatting float point
printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i);
#else
printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
#endif
break;
case AArch64_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != AArch64_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
if (op->mem.index != AArch64_REG_INVALID)
printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);

break;
case AArch64_OP_CIMM:
printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm);
break;
case AArch64_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != AArch64_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
if (op->mem.index != AArch64_REG_INVALID)
printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
if (ins->detail->aarch64.post_index)
printf("\t\t\tpost-indexed: true\n");

break;
case AArch64_OP_SME_MATRIX:
printf("\t\toperands[%u].type: SME_MATRIX\n", i);
printf("\t\toperands[%u].sme.type: %d\n", i, op->sme.type);

if (op->sme.tile != AArch64_REG_INVALID)
printf("\t\toperands[%u].sme.tile: %s\n", i, cs_reg_name(handle, op->sme.tile));
if (op->sme.slice_reg != AArch64_REG_INVALID)
printf("\t\toperands[%u].sme.slice_reg: %s\n", i, cs_reg_name(handle, op->sme.slice_reg));
if (op->sme.slice_offset.imm != -1 || op->sme.slice_offset.imm_range.first != -1) {
printf("\t\toperands[%u].sme.slice_offset: ", i);
if (op->sme.has_range_offset)
printf("%hhd:%hhd\n", op->sme.slice_offset.imm_range.first, op->sme.slice_offset.imm_range.offset);
else
printf("%d\n", op->sme.slice_offset.imm);
}
if (op->sme.slice_reg != AArch64_REG_INVALID || op->sme.slice_offset.imm != -1)
printf("\t\toperands[%u].sme.is_vertical: %s\n", i, (op->sme.is_vertical ? "true" : "false"));
break;
case AArch64_OP_CIMM:
printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm);
break;
case AArch64_OP_SYSREG:
printf("\t\toperands[%u].type: SYS REG:\n", i);
switch (op->sysop.sub_type) {
default:
printf("Sub type %d not handled.\n", op->sysop.sub_type);
break;
case AArch64_OP_REG_MRS:
printf("\t\toperands[%u].type: REG_MRS = 0x%x\n", i, op->reg);
printf("\t\toperands[%u].subtype: REG_MRS = 0x%x\n", i, op->sysop.reg.sysreg);
break;
case AArch64_OP_REG_MSR:
printf("\t\toperands[%u].type: REG_MSR = 0x%x\n", i, op->reg);
printf("\t\toperands[%u].subtype: REG_MSR = 0x%x\n", i, op->sysop.reg.sysreg);
break;
case AArch64_OP_PSTATEIMM0_1:
printf("\t\toperands[%u].type: PSTATE = 0x%x\n", i, op->sysop.alias.pstateimm0_1);
case AArch64_OP_TLBI:
printf("\t\toperands[%u].subtype TLBI = 0x%x\n", i, op->sysop.reg.tlbi);
break;
case AArch64_OP_PSTATEIMM0_15:
printf("\t\toperands[%u].type: PSTATE = 0x%x\n", i, op->sysop.alias.pstateimm0_15);
case AArch64_OP_IC:
printf("\t\toperands[%u].subtype IC = 0x%x\n", i, op->sysop.reg.ic);
break;
}
break;
case AArch64_OP_SYSALIAS:
printf("\t\toperands[%u].type: SYS ALIAS:\n", i);
switch (op->sysop.sub_type) {
default:
printf("Sub type %d not handled.\n", op->sysop.sub_type);
break;
case AArch64_OP_SVCR:
if(op->sysop.alias.svcr == AArch64_SVCR_SVCRSM)
printf("\t\t\toperands[%u].svcr: BIT = SM\n", i);
else if(op->sysop.alias.svcr == AArch64_SVCR_SVCRZA)
printf("\t\t\toperands[%u].svcr: BIT = ZA\n", i);
else if(op->sysop.alias.svcr == AArch64_SVCR_SVCRSMZA)
printf("\t\t\toperands[%u].svcr: BIT = SM & ZA\n", i);
break;
case AArch64_OP_AT:
printf("\t\toperands[%u].type: AT = 0x%x\n", i, op->sysop.alias.at);
printf("\t\toperands[%u].subtype AT = 0x%x\n", i, op->sysop.alias.at);
break;
case AArch64_OP_DB:
printf("\t\toperands[%u].subtype DB = 0x%x\n", i, op->sysop.alias.db);
break;
case AArch64_OP_DC:
printf("\t\toperands[%u].subtype DC = 0x%x\n", i, op->sysop.alias.dc);
break;
case AArch64_OP_ISB:
printf("\t\toperands[%u].subtype ISB = 0x%x\n", i, op->sysop.alias.isb);
break;
case AArch64_OP_TSB:
printf("\t\toperands[%u].subtype TSB = 0x%x\n", i, op->sysop.alias.tsb);
break;
case AArch64_OP_PRFM:
printf("\t\toperands[%u].type: PREFETCH = 0x%x\n", i, op->sysop.alias.prfm);
printf("\t\toperands[%u].subtype PRFM = 0x%x\n", i, op->sysop.alias.prfm);
break;
case AArch64_OP_DB:
printf("\t\toperands[%u].type: BARRIER = 0x%x\n", i, op->sysop.alias.db);
case AArch64_OP_SVEPRFM:
printf("\t\toperands[%u].subtype SVEPRFM = 0x%x\n", i, op->sysop.alias.sveprfm);
break;
case AArch64_OP_RPRFM:
printf("\t\toperands[%u].subtype RPRFM = 0x%x\n", i, op->sysop.alias.rprfm);
break;
case AArch64_OP_PSTATEIMM0_15:
printf("\t\toperands[%u].subtype PSTATEIMM0_15 = 0x%x\n", i, op->sysop.alias.pstateimm0_15);
break;
case AArch64_OP_PSTATEIMM0_1:
printf("\t\toperands[%u].subtype PSTATEIMM0_1 = 0x%x\n", i, op->sysop.alias.pstateimm0_1);
break;
case AArch64_OP_PSB:
printf("\t\toperands[%u].subtype PSB = 0x%x\n", i, op->sysop.alias.psb);
break;
case AArch64_OP_BTI:
printf("\t\toperands[%u].subtype BTI = 0x%x\n", i, op->sysop.alias.bti);
break;
case AArch64_OP_SVEPREDPAT:
printf("\t\toperands[%u].subtype SVEPREDPAT = 0x%x\n", i, op->sysop.alias.svepredpat);
break;
case AArch64_OP_SVEVECLENSPECIFIER:
printf("\t\toperands[%u].subtype SVEVECLENSPECIFIER = 0x%x\n", i, op->sysop.alias.sveveclenspecifier);
break;
// TODO Add the others.
}
break;
case AArch64_OP_SYSIMM:
printf("\t\toperands[%u].type: SYS IMM:\n", i);
switch(op->sysop.sub_type) {
default:
printf("Sub type %d not handled.\n", op->sysop.sub_type);
break;
case AArch64_OP_EXACTFPIMM:
printf("\t\toperands[%u].subtype EXACTFPIMM = %d\n", i, op->sysop.imm.exactfpimm);
break;
case AArch64_OP_DBNXS:
printf("\t\toperands[%u].subtype DBNXS = %d\n", i, op->sysop.imm.dbnxs);
break;
}
break;
}

access = op->access;
switch(access) {
default:
Expand All @@ -116,11 +206,11 @@ static void print_insn_detail(cs_insn *ins)
printf("\t\toperands[%u].access: READ | WRITE\n", i);
break;
}

if (op->shift.type != AArch64_SFT_INVALID &&
op->shift.value)
op->shift.value)
printf("\t\t\tShift: type = %u, value = %u\n",
op->shift.type, op->shift.value);
op->shift.type, op->shift.value);

if (op->ext != AArch64_EXT_INVALID)
printf("\t\t\tExt: %u\n", op->ext);
Expand All @@ -136,9 +226,9 @@ static void print_insn_detail(cs_insn *ins)
printf("\tUpdate-flags: True\n");

if (ins->detail->writeback)
printf("\tWrite-back: %s\n", aarch64->post_index ? "Post" : "Pre");
printf("\tWrite-back: True\n");

if (aarch64->cc)
if (aarch64->cc != AArch64CC_Invalid)
printf("\tCode-condition: %u\n", aarch64->cc);

// Print out all registers accessed by this instruction (either implicit or explicit)
Expand Down Expand Up @@ -248,4 +338,3 @@ int main()

return 0;
}

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