Catch up all eDSL files to rehome

calyx-py/calyx/builder.py

@@ -537,7 +537,7 @@ def decr(self, reg, width, val=1, cellname=None):
             decr_group.done = reg.done
         return decr_group
 
-    def insert_reg_store(self, reg, val, groupname=None):
+    def reg_store(self, reg, val, groupname=None):
         """Stores a value in a register.
         1. Within component {self}, creates a group.
         2. Within the group, sets the register {reg} to {val}.
@@ -616,81 +616,77 @@ def mem_write_seq_d1_to_reg(self, mem, reg, groupname=None):
             write_grp.done = reg.done
         return write_grp
 
+    def mem_store_seq_d1(self, mem, i, val, groupname=None):
+        """Given a seq_mem_d1, stores a value into memory at address i.
 
-def mem_store_seq_d1(self, mem, i, val, groupname=None):
-    """Given a seq_mem_d1, stores a value into memory at address i.
+        1. Within component {self}, creates a group.
+        2. Within the group, reads from {val}.
+        3. Writes the value into memory {mem} at address i.
+        4. Returns the group.
+        """
+        assert mem.is_seq_mem_d1()
+        groupname = groupname or f"{mem.name()}_store"
+        with self.group(groupname) as store_grp:
+            mem.addr0 = i
+            mem.write_en = 1
+            mem.write_data = val
+            store_grp.done = mem.write_done
+        return store_grp
 
-    1. Within component {self}, creates a group.
-    2. Within the group, reads from {val}.
-    3. Writes the value into memory {mem} at address i.
-    4. Returns the group.
-    """
-    assert mem.is_seq_mem_d1()
-    groupname = groupname or f"{mem.name()}_store"
-    with self.group(groupname) as store_grp:
-        mem.addr0 = i
-        mem.write_en = 1
-        mem.write_data = val
-        store_grp.done = mem.write_done
-    return store_grp
-
-
-def insert_mem_load_to_mem(self, mem, i, ans, j, groupname=None):
-    """Loads a value from one std_mem_d1 memory into another.
-    1. Within component {self}, creates a group.
-    2. Within the group, reads from memory {mem} at address {i}.
-    3. Writes the value into memory {ans} at address {j}.
-    4. Returns the group.
-    """
-    assert mem.is_std_mem_d1() and ans.is_std_mem_d1()
-    groupname = groupname or f"{mem.name()}_load_to_mem"
-    with self.group(groupname) as load_grp:
-        mem.addr0 = i
-        ans.write_en = 1
-        ans.addr0 = j
-        ans.write_data = mem.read_data
-        load_grp.done = ans.done
-    return load_grp
-
-
-def insert_add_store_in_reg(self, cellname, left, right, ans_reg=None):
-    """Inserts wiring into component {self} to compute {left} + {right} and
-      store it in {ans_reg}.
-    1. Within component {self}, creates a group called {cellname}_group.
-    2. Within {group}, create a cell {cellname} that computes sums.
-    3. Puts the values of {left} and {right} into the cell.
-    4. Then puts the answer of the computation into {ans_reg}.
-    4. Returns the summing group and the register.
-    """
-    add_cell = self.add(32, cellname)
-    ans_reg = ans_reg or self.reg(f"reg_{cellname}", 32)
-    with self.group(f"{cellname}_group") as adder_group:
-        add_cell.left = left
-        add_cell.right = right
-        ans_reg.write_en = 1
-        ans_reg.in_ = add_cell.out
-        adder_group.done = ans_reg.done
-    return adder_group, ans_reg
-
-
-def insert_sub_store_in_reg(self, left, right, cellname, width, ans_reg=None):
-    """Adds wiring into component {self} to compute {left} - {right}
-    and store it in {ans_reg}.
-    1. Within component {self}, creates a group called {cellname}_group.
-    2. Within {group}, create a cell {cellname} that computes differences.
-    3. Puts the values of {left} and {right} into {cell}.
-    4. Then puts the answer of the computation into {ans_reg}.
-    4. Returns the subtracting group and the register.
-    """
-    sub_cell = self.sub(width, cellname)
-    ans_reg = ans_reg or self.reg(f"reg_{cellname}", width)
-    with self.group(f"{cellname}_group") as sub_group:
-        sub_cell.left = left
-        sub_cell.right = right
-        ans_reg.write_en = 1
-        ans_reg.in_ = sub_cell.out
-        sub_group.done = ans_reg.done
-    return sub_group, ans_reg
+    def mem_load_to_mem(self, mem, i, ans, j, groupname=None):
+        """Loads a value from one std_mem_d1 memory into another.
+        1. Within component {self}, creates a group.
+        2. Within the group, reads from memory {mem} at address {i}.
+        3. Writes the value into memory {ans} at address {j}.
+        4. Returns the group.
+        """
+        assert mem.is_std_mem_d1() and ans.is_std_mem_d1()
+        groupname = groupname or f"{mem.name()}_load_to_mem"
+        with self.group(groupname) as load_grp:
+            mem.addr0 = i
+            ans.write_en = 1
+            ans.addr0 = j
+            ans.write_data = mem.read_data
+            load_grp.done = ans.done
+        return load_grp
+
+    def add_store_in_reg(self, cellname, left, right, ans_reg=None):
+        """Inserts wiring into component {self} to compute {left} + {right} and
+        store it in {ans_reg}.
+        1. Within component {self}, creates a group called {cellname}_group.
+        2. Within {group}, create a cell {cellname} that computes sums.
+        3. Puts the values of {left} and {right} into the cell.
+        4. Then puts the answer of the computation into {ans_reg}.
+        4. Returns the summing group and the register.
+        """
+        add_cell = self.add(32, cellname)
+        ans_reg = ans_reg or self.reg(f"reg_{cellname}", 32)
+        with self.group(f"{cellname}_group") as adder_group:
+            add_cell.left = left
+            add_cell.right = right
+            ans_reg.write_en = 1
+            ans_reg.in_ = add_cell.out
+            adder_group.done = ans_reg.done
+        return adder_group, ans_reg
+
+    def sub_store_in_reg(self, left, right, cellname, width, ans_reg=None):
+        """Adds wiring into component {self} to compute {left} - {right}
+        and store it in {ans_reg}.
+        1. Within component {self}, creates a group called {cellname}_group.
+        2. Within {group}, create a cell {cellname} that computes differences.
+        3. Puts the values of {left} and {right} into {cell}.
+        4. Then puts the answer of the computation into {ans_reg}.
+        4. Returns the subtracting group and the register.
+        """
+        sub_cell = self.sub(width, cellname)
+        ans_reg = ans_reg or self.reg(f"reg_{cellname}", width)
+        with self.group(f"{cellname}_group") as sub_group:
+            sub_cell.left = left
+            sub_cell.right = right
+            ans_reg.write_en = 1
+            ans_reg.in_ = sub_cell.out
+            sub_group.done = ans_reg.done
+        return sub_group, ans_reg
 
 
 def as_control(obj):

calyx-py/calyx/queue_call.py

@@ -1,6 +1,5 @@
 # pylint: disable=import-error
 import calyx.builder as cb
-import calyx.builder_util as util
 
 MAX_CMDS = 15
 ANS_MEM_LEN = 10
@@ -22,7 +21,7 @@ def insert_raise_err_if_i_eq_max_cmds(prog):
     err = raise_err_if_i_eq_max_cmds.reg("err", 1, is_ref=True)
 
     i_eq_max_cmds = raise_err_if_i_eq_max_cmds.eq_use(i, MAX_CMDS, 32)
-    raise_err = util.insert_reg_store(raise_err_if_i_eq_max_cmds, err, 1, "raise_err")
+    raise_err = raise_err_if_i_eq_max_cmds.reg_store(err, 1, "raise_err")
 
     raise_err_if_i_eq_max_cmds.control += [
         cb.if_(
@@ -84,12 +83,10 @@ def insert_main(prog, queue):
     err_eq_0 = main.eq_use(err.out, 0, 1)  # is `err` flag down?
     cmd_le_1 = main.le_use(cmd.out, 1, 32)  # cmd <= 1
 
-    read_cmd = util.mem_read_seq_d1(main, commands, i.out, "read_cmd_phase1")
-    write_cmd_to_reg = util.mem_write_seq_d1_to_reg(
-        main, commands, cmd, "write_cmd_phase2"
-    )
+    read_cmd = main.mem_read_seq_d1(commands, i.out, "read_cmd_phase1")
+    write_cmd_to_reg = main.mem_write_seq_d1_to_reg(commands, cmd, "write_cmd_phase2")
 
-    write_ans = util.mem_store_seq_d1(main, ans_mem, j.out, ans.out, "write_ans")
+    write_ans = main.mem_store_seq_d1(ans_mem, j.out, ans.out, "write_ans")
 
     main.control += [
         cb.while_(

calyx-py/test/correctness/arbiter_6.py

@@ -1,5 +1,4 @@
 # pylint: disable=import-error
-import calyx.builder_util as util
 import calyx.builder as cb
 
 
@@ -36,21 +35,21 @@ def add_wrap2(prog):
     j_lt_8_cell, j_lt_8_group = wrap.lt_use(j, 8, 32)
 
     # Load `j` unchanged into `j_mod_4`.
-    unchanged = util.insert_reg_store(wrap, j_mod_4, j, "j_unchanged")
+    unchanged = wrap.reg_store(j_mod_4, j, "j_unchanged")
 
     # Wiring to perform j-4 and j-8. Either of these will store the result in `j_mod_4`.
-    j_minus_4, j_mod_4 = util.insert_sub_store_in_reg(
-        wrap, j, cb.const(32, 4), "j_minus_4", 32, j_mod_4
+    j_minus_4, j_mod_4 = wrap.sub_store_in_reg(
+        j, cb.const(32, 4), "j_minus_4", 32, j_mod_4
     )
-    j_minus_8, j_mod_4 = util.insert_sub_store_in_reg(
-        wrap, j, cb.const(32, 8), "j_minus_8", 32, j_mod_4
+    j_minus_8, j_mod_4 = wrap.sub_store_in_reg(
+        j, cb.const(32, 8), "j_minus_8", 32, j_mod_4
     )
 
     load_from_mems = [
         # Add wiring to load the value `j_mod_4` from all of the memory cells.
         # We'll have to invoke the correct one of these groups later on.
-        util.insert_mem_load_to_mem(
-            wrap, mems[i], j_mod_4.out, ans, cb.const(32, 0), f"load_from_mem{i}"
+        wrap.mem_load_to_mem(
+            mems[i], j_mod_4.out, ans, cb.const(32, 0), f"load_from_mem{i}"
         )
         for i in range(6)
     ]
@@ -132,16 +131,16 @@ def add_wrap3(prog):
     j_lt_4_cell, j_lt_4_group = wrap.lt_use(j, 4, 32)
 
     # Load `j` unchanged into `j_mod_4`.
-    unchanged = util.insert_reg_store(wrap, j_mod_4, j, "j_unchanged")
+    unchanged = wrap.reg_store(j_mod_4, j, "j_unchanged")
 
     # Wiring to perform j-4 and store the result in `j_mod_4`.
-    subcell, j_mod_4 = util.insert_sub_store_in_reg(
-        wrap, j, cb.const(32, 4), "j_minus_4", 32, j_mod_4
+    subcell, j_mod_4 = wrap.sub_store_in_reg(
+        j, cb.const(32, 4), "j_minus_4", 32, j_mod_4
     )
 
     emit_from_mems = [
-        util.insert_mem_load_to_mem(
-            wrap, mems[i], j_mod_4.out, ans, cb.const(32, 0), f"load_from_mem{i}"
+        wrap.mem_load_to_mem(
+            mems[i], j_mod_4.out, ans, cb.const(32, 0), f"load_from_mem{i}"
         )
         for i in range(6)
     ]

calyx-py/test/correctness/fifo.py

@@ -1,6 +1,5 @@
 # pylint: disable=import-error
 import calyx.builder as cb
-import calyx.builder_util as util
 import calyx.queue_call as qc
 
 MAX_QUEUE_LEN = 10
@@ -51,20 +50,16 @@ def insert_fifo(prog, name):
     len_decr = fifo.decr(len, 32)  # len--
 
     # Cells and groups to modify flags, which are registers
-    flash_write = util.insert_reg_store(fifo, write, 0, "flash_write")  # write := 0
-    flash_read = util.insert_reg_store(fifo, read, 0, "flash_read")  # read := 0
-    raise_err = util.insert_reg_store(fifo, err, 1, "raise_err")  # err := 1
-    flash_ans = util.insert_reg_store(fifo, ans, 0, "flash_ans")  # ans := 0
+    flash_write = fifo.reg_store(write, 0, "flash_write")  # write := 0
+    flash_read = fifo.reg_store(read, 0, "flash_read")  # read := 0
+    raise_err = fifo.reg_store(err, 1, "raise_err")  # err := 1
+    flash_ans = fifo.reg_store(ans, 0, "flash_ans")  # ans := 0
 
     # Load and store into an arbitary slot in memory
-    write_to_mem = util.mem_store_seq_d1(
-        fifo, mem, write.out, cmd, "write_payload_to_mem"
-    )
-    read_from_mem = util.mem_read_seq_d1(
-        fifo, mem, read.out, "read_payload_from_mem_phase1"
-    )
-    write_to_ans = util.mem_write_seq_d1_to_reg(
-        fifo, mem, ans, "read_payload_from_mem_phase2"
+    write_to_mem = fifo.mem_store_seq_d1(mem, write.out, cmd, "write_payload_to_mem")
+    read_from_mem = fifo.mem_read_seq_d1(mem, read.out, "read_payload_from_mem_phase1")
+    write_to_ans = fifo.mem_write_seq_d1_to_reg(
+        mem, ans, "read_payload_from_mem_phase2"
     )
 
     fifo.control += [

calyx-py/test/correctness/pifo.py

@@ -1,7 +1,6 @@
 # pylint: disable=import-error
 import fifo
 import calyx.builder as cb
-import calyx.builder_util as util
 import calyx.queue_call as qc
 
 MAX_QUEUE_LEN = 10
@@ -120,9 +119,9 @@ def insert_pifo(prog, name, queue_l, queue_r, boundary):
     err_neq_0 = pifo.neq_use(err.out, cb.const(1, 0), 1)
 
     flip_hot = pifo.bitwise_flip_reg(hot, 1)
-    raise_err = util.insert_reg_store(pifo, err, 1, "raise_err")  # err := 1
-    lower_err = util.insert_reg_store(pifo, err, 0, "lower_err")  # err := 0
-    flash_ans = util.insert_reg_store(pifo, ans, 0, "flash_ans")  # ans := 0
+    raise_err = pifo.reg_store(err, 1, "raise_err")  # err := 1
+    lower_err = pifo.reg_store(err, 0, "lower_err")  # err := 0
+    flash_ans = pifo.reg_store(ans, 0, "flash_ans")  # ans := 0
 
     len_incr = pifo.incr(len, 32)  # len++
     len_decr = pifo.decr(len, 32)  # len--

calyx-py/test/correctness/reduction_tree.py

@@ -1,6 +1,5 @@
 # pylint: disable=import-error
 from typing import List
-import calyx.builder_util as util
 import calyx.builder as cb
 
 
@@ -24,11 +23,9 @@ def add_tree(prog):
     # Into the component `tree`, add the wiring for three adder groups that will
     # use the tree to perform their additions.
     # These need to be orchestrated in the control below.
-    add_l0_l1, left = util.insert_add_store_in_reg(tree, "add_l0_l1", leaf0, leaf1)
-    add_l2_l3, right = util.insert_add_store_in_reg(tree, "add_l2_l3", leaf2, leaf3)
-    add_l_r_nodes, root = util.insert_add_store_in_reg(
-        tree, "add_l_r", left.out, right.out
-    )
+    add_l0_l1, left = tree.add_store_in_reg("add_l0_l1", leaf0, leaf1)
+    add_l2_l3, right = tree.add_store_in_reg("add_l2_l3", leaf2, leaf3)
+    add_l_r_nodes, root = tree.add_store_in_reg("add_l_r", left.out, right.out)
 
     # Continuously output the value of the root register.
     # It is the invoker's responsibility to ensure that the tree is done