Passes!

calyx-py/calyx/builder.py

@@ -312,6 +312,10 @@ def and_(self, name: str, size: int) -> CellBuilder:
         """Generate a StdAnd cell."""
         return self.cell(name, ast.Stdlib.op("and", size, False))
 
+    def not_(self, name: str, size: int) -> CellBuilder:
+        """Generate a StdNot cell."""
+        return self.cell(name, ast.Stdlib.op("not", size, False))
+
     def pipelined_mult(self, name: str) -> CellBuilder:
         """Generate a pipelined multiplier."""
         self.prog.import_("primitives/pipelined.futil")

calyx-py/calyx/builder_util.py

@@ -109,6 +109,20 @@ def insert_sub(comp: cb.ComponentBuilder, left, right, cellname, width):
     return insert_comb_group(comp, left, right, sub_cell, f"{cellname}_group")
 
 
+def insert_bitwise_flip_reg(comp: cb.ComponentBuilder, reg, cellname, width):
+    """Inserts wiring into component {comp} to put the bitwise flip of {reg} into {reg}.
+
+    Returns a handle to the group that does this.
+    """
+    not_cell = comp.not_(cellname, width)
+    with comp.group(f"{cellname}_group") as not_group:
+        not_cell.in_ = reg.out
+        reg.write_en = 1
+        reg.in_ = not_cell.out
+        not_group.done = reg.done
+    return not_group
+
+
 def insert_incr(comp: cb.ComponentBuilder, reg, cellname, val=1):
     """Inserts wiring into component {comp} to increment register {reg} by {val}.
     1. Within component {comp}, creates a group called {cellname}_group.
@@ -230,26 +244,6 @@ def mem_store_seq_d1(comp: cb.ComponentBuilder, mem, i, val, group):
     return store_grp
 
 
-def reg_swap(comp: cb.ComponentBuilder, a, b, group):
-    """Swaps the values of two registers.
-    1. Within component {comp}, creates a group called {group}.
-    2. Reads the value of {a} into a temporary register.
-    3. Writes the value of {b} into {a}.
-    4. Writes the value of the temporary register into {b}.
-    5. Returns the group that does this.
-    """
-    with comp.group(group) as swap_grp:
-        tmp = comp.reg("tmp", 1)
-        tmp.write_en = 1
-        tmp.in_ = a.out
-        a.write_en = 1
-        a.in_ = b.out
-        b.write_en = 1
-        b.in_ = tmp.out
-        swap_grp.done = b.done
-    return swap_grp
-
-
 def insert_mem_load_to_mem(comp: cb.ComponentBuilder, mem, i, ans, j, group):
     """Loads a value from one std_mem_d1 memory into another.
     1. Within component {comp}, creates a group called {group}.

calyx-py/test/correctness/pifo.data

@@ -42,4 +42,4 @@
       "width": 32
     }
   }
-}
+}

calyx-py/test/correctness/pifo.py

@@ -43,7 +43,6 @@ def insert_pifo(prog, name):
     `fifo_0` and `fifo_1`.
     Maintain additionally a register that points to which of these FIFOs is "hot".
     Start off with `hot` pointing to `fifo_0` (arbitrarily).
-    Maintain `cold` that points to the other fifo.
 
     - `push(v, PIFO)`:
        + If len(PIFO) = 10, raise an "overflow" err and exit.
@@ -56,11 +55,11 @@ def insert_pifo(prog, name):
     - `pop(PIFO)`:
        + If `len(PIFO)` = 0, raise an "underflow" flag and exit.
        + Try `pop(FIFO_{hot})`.
-         * If it succeeds it will return a value `v`; just propagate `v`. Also flip
-           `hot` and `cold`.
-         * If it fails because of underflow, return `pop(FIFO_{cold})`.
+         * If it succeeds it will return a value `v`; just propagate `v`.
+            Also flip `hot` so it points to the other FIFO.
+         * If it fails because of underflow, return `pop(FIFO_{not-hot})`.
            If the _second_ pop also fails, propagate the error.
-           Leave `hot` and `cold` as they were.
+           Leave `hot` as it was.
     """
 
     pifo: cb.ComponentBuilder = prog.component(name)
@@ -85,7 +84,6 @@ def insert_pifo(prog, name):
 
     # Two registers that mark the next FIFO to `pop` from
     hot = pifo.reg("hot", 1)
-    cold = pifo.reg("cold", 1)
 
     # Some equality checks.
     hot_eq_0 = util.insert_eq(pifo, hot.out, cb.const(1, 0), "hot_eq_0", 1)  # hot == 0
@@ -101,7 +99,7 @@ def insert_pifo(prog, name):
         pifo, err.out, cb.const(1, 0), "err_neq_0", 1
     )  # err != 0
 
-    swap = util.reg_swap(pifo, hot, cold, "swap")  # Swap `hot` and `cold`.
+    flip_hot = util.insert_bitwise_flip_reg(pifo, hot, "flip_hot", 1)  # Flip `hot`.
     raise_err = util.insert_reg_store(pifo, err, 1, "raise_err")  # set `err` to 1
     lower_err = util.insert_reg_store(pifo, err, 0, "lower_err")  # set `err` to 0
     zero_out_ans = util.insert_reg_store(pifo, ans, 0, "zero_out_ans")  # zero out `ans`
@@ -164,8 +162,9 @@ def insert_pifo(prog, name):
                                             err_eq_0[1],
                                             [  # `fifo_0` succeeded.
                                                 # Its answer is our answer.
-                                                swap
-                                                # We'll just swap `hot` and `cold`.
+                                                flip_hot
+                                                # We'll just make `hot` point
+                                                # to the other FIFO.
                                             ],
                                         ),
                                     ),
@@ -199,7 +198,7 @@ def insert_pifo(prog, name):
                                         cb.if_(
                                             err_eq_0[0].out,
                                             err_eq_0[1],
-                                            [swap],
+                                            [flip_hot],
                                         ),
                                     ),
                                 ],